iosr-JVSP   Volume-7 ~ Issue-4 ~ Jul-Aug 2017

ABSTRACT: One of the biggest and important issues in the video watermarking is the distortion and attacks. The attacks and distortion affect the digital watermarking. Watermarking is an embedding process. With the help of watermarking, we insert the data into the digital objects. There are few methods are available for authentication of data, securing/protection of data. The watermarking technique also provides the data security, copyright protection and authentication of the data. Watermarking provides a comfortable life to authorized users. In my proposed work, we are working on distorted watermarked video. The distortion is present on the watermarked video is rational 7th and 8th order distortion model...........

Keywords: Video watermarking, Rational 7th and 8th distortion model, Correlation, SSIM, MSE, BER.

[1] V.M. Potdar, S. Han, and E. Chang, "A Survey of Digital Image Watermarking Techniques", INDIN '05. 2005 3rd IEEE International Conference on Industrial Informatics, 2005, pp. 709- 716, 2005.
[2] P. Singh, R.S. Chadha, "A Survey of Digital Watermarking Techniques, Applications and Attacks" International Journal of Engineering and Innovative Technology, vol. 2, no.9, pp. 165- 175, 2013.
[3] G.S. Bhatia, K. Kaur, "Video Watermarking using YcbCr and RLE", International Journal of Engineering and Technology, vol. 03, no.08, pp. 1025- 1030, 2016.

[4] D. Claus and A.W. Fitzgibbon, "A Rational Function Lens Distortion Model for General Cameras", Computer Vision and Pattern Recognition, 2005. CVPR 2005. IEEE Computer Society Conference on", Volume 1, Pages 213-219, July 2005.

[5] A. Agrawal, "Securing Video Data: A Critical Review", International Journal of Advanced Research in Computer and Communication Engineering, vol. 3, no.5, pp6610-6613, 2014.

ABSTRACT: This paper presents a new topology to implement MOS current mod logic (MCML) tri-state buffers. In Mos current mode logic (MCML) current section is improves the performance and maintains low power of the circuit. MCML circuits contains true differential operation by which provides the feature of low noise level generation and static power dissipation. So the amount of current drawn from the power supply does not depends on the switching activity. Due to this MOS current mode logic (MCML) circuits have been useful for developing analog and mixed signal IC's. The implementing of MCML D-flip flop and Frequency divider done by using MCML D-latches.............

Keywords: Mos current mode logic (MCML), Tri-state buffer, D-latch, D-flip flop, low power.

[1]. Tajalli A, Vittoz E.,Leblebici Y, Brauer E.J. "Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept" Solid State Circuits Conference.IEEE International Conference,sept -2007 Pages:304 – 307.

[2]. Sumathi,M. "Performance and analysis of cml logic gates and latches"Microwave,Antenna,Propagation and EMC Technologies for Wireless Communications, IEEE International Conference pages: 1428 – 1432,Aug-2007.

[3]. Ni Haiyan ; Hu Jianping , "The layout implementations of high-speed low-power MCML cells"Electronics, Communications and Control (ICECC),IEEE International Conference Page(s): 2936 – 2939, sept-2011.
[4]. H. Knapp, H.-D. Wohlmuth, M. Wurzer, et al., "25GHz Static Frequency Divider and 25Gb/s Multiplexer in 0.12 μm CMOS," ISSCC Dig.Of Tech. Papers, pp. 302-468, Feb.2002.
[5]. M. Tie bout, "A 480μW 2GHz ultra low power dual-modulus prescaler in μm standard CMOS," IEEE International Symposium on Circuitsand Systems Proceedings, vol. 5, pp. 741-744, May. 2000.

ABSTRACT: To achieve the reduction of power consumption, optimizations are required at various levels of the design steps such as algorithm, architecture, logic and circuit & process techniques. This paper considers the two logic level approaches for low power digital design. Optimization techniques are carried to reduce switching activity power of individual logic-gates. we can reduce the power by using either circuit level optimization or logical level optimization............

Keywords: PASTA, Modified GDI logic, Optimized XOR and half adder, MVL, Tanner toolv14.11.

[1] Arkadiy Morgenshtein, Viacheslav Yuzhaninov, Alexey Kovshilovsky and Alexander Fish, "Full-Swing Gate Diffusion Input logic-Case-study of low-power CLA adder design", Integration, theVLSI journal, Vol. 47, 62-70, 2014.
[2] Basant Kumar, M. and Sujit Kumar, P., "Area-Delay-Power Efficient Carry-Select Adder", IEEE Transactions on Circuits and Systems-II: Express Briefs, Vol. 61, No. 6, June 2014.
[3] Geetha Priya, M. and Baskaran, K., "Low Power Full Adder with Reduced Transistor Count". International Journal of Engineering Trends and Technology (IJETT)-Volume 4 No. 5, May 2013.
[4] Kalavathidevi, T. and Venkatesh, C., "Gate Diffusion Input (GDI) Circuits Based Low Power VLSI Architecture for a Viterbi Decoder", Iranian Journal of Electrical and Computer Engineering (ACECR), Vol. 10, No. 2, 2011.
[5] Kapil Mangla and Shashank Saxena, "Analysis of Different CMOS Full Adder Circuits Based on Various Parameters for Low Voltage VLSI Design", International Journal of Engineering and Technical Research (IJETR), Vol. 3, No-5, May 2015.