iosr-JVSP   Volume-3 ~ Issue-5

ABSTRACT:Nowadays Electronic devices are portable which requires low power/low voltage requirement to maximize the battery lifetime. We propose Schmitt Trigger based SRAM bitcell that can operate on low supply voltages. The proposed Schmitt trigger SRAM bitcell resolves the fundamental conflicting design requirement of read versus write operation of conventional 6T bitcell and it gives better read-stability as well as better write ability compared to the other bitcell. This work is executed under the Mentor Graphics EDA tools in 350nm, 250nm CMOS technology. ST-2 cell consumes less power than ST-1 cell.

Keywords: low voltage SRAM, Schmitt Trigger (ST), voltage scaling

[2] A. Bhavnagarwala, X. Tang, and J. Meindl, "The impact of intrinsic device fluctuations on CMOS SRAM cell stability", IEEE J.
Solid-state Circuits, vol. 36, no. 4, Apr. 2001.
[3] S. Mukhopadhyay, H. Mahmoodi, and K.Roy, "Modeling of failure probability and statistical design of SRAM array for yield
enhancement in nanoscaled CMOS", IEEE Trans. Computer-Aided Design. Dec. 2005
[4] N. Yoshinobu, H. Masahi, K. Takayuki, and K. Itoh, "Review and future prospects of low-voltage RAM circuits", IBM J. Res.
Devel, vol. 47, 2003
[5] M. M. Khellah, A. Keshavarzi, D. Somasekhar, T. Karnik, and V. De, "Read and write circuit assist techniques for improving
Vccmin off dense 6T SRAM cell", in proc. Int. Conf. Integr. Circuit Design Technol., June. 2008,pp.
[6] B. Zhai, D. Blaauw, D. Sylvester, and S. Hanson, "A sub-200 mV 6T SRAM in 0.13um CMOS", in proc. Int. Solid state Circuits
conf. Feb. 2007.
[7] L. Chang, D. Fried, J. Hergenrother, J. Sleight, R. Dennard, R.R. Montoye, L. Sekaric, S. McNab, W. Topol, C. Adams, K. Guarini,
and W. Haensch, "Stable SRAM cell design for the 32nm node and beyond" , in Proc.VLSI sym.
[8] N. Verma and A. P.Chandrakasan, "65nm 8T sub-Vt SRAM employing sense-amplifier redundancy", in Proc. Int. Solid State
Circuits Conf Feb. 2007.
[9] V. Ramadurai, R. Joshi, and R. Kanj, "A disturb decoupled column select 8T SRAM cell", in Proc. Custom Integr. Circuits Conf.
Sept 2007.

ABSTRACT:Digital signal processing (DSP) is concerned with the representation of discrete time signals by a sequence of numbers or symbols and the processing of these signals. Digital signal processing and analog signal processing are subfields of signal processing. DSP includes subfields like: audio and speech signal processing, sonar and radar signal processing, sensor array processing, spectral estimation, statistical signal processing, digital image processing, signal processing for communications, control of systems, biomedical signal processing, seismic data processing, etc. in this paper mainly concentrate on array signal processing. Array processing involves combining all sensor outputs in some optimal manner so that the coherent signals emitted by the source are received and all other inputs are maximally discarded. Beam forming algorithms are the foundation for all array processing techniques since this is an effective technique to estimate direction of arrival (DOA). The areas in which beam formers play an important role include radar, sonar, seismology etc. in this paper presents comparative study of beam forming techniques and its implementation on ADSP TS 201 processor

Keywords: signal-to-interference-plus-noise ratio (SINR), direction of arrival (DOA), Minimum Variance Distortion less Response (MVDR),

[1] H.L. Van Trees, "Optimum Array Processing - Part IV of Detection, Estimation and Modulation Theory," John Wiley & Sons Inc.,
New York, 2002.
[2] D. Johnson and D. Dudgeon, "Array Signal Processing Concepts and Techniques," Prentice Hall, Upper Saddle River, NJ, 1993.
[3] Van Veen, D.,Buckley, M., "Beam forming: A versatile approach to spatial filtering", IEEE ASSP Magazine, April 1988.
[4] Hamid Krim, Mats Viberg, "Two decades of array signal processing research", IEEE signal Processing Magazine, July 1996.
[5] www.analog.com/en/embedded.../tigersharc/processors/.../index.html

ABSTRACT: In this paper, IMAGE Compression technique is developed with DWT (discrete wavelet transformation). SPIHT Algorithm is used in the dwt process. hardware architecture of 2d dwt have been implemented as a coprocessor in an embedded system. In this IMAGE Compression technique the 2d_dwt is generated by using cascading of two 1d-dwt. This DWT-based image processing system is developed on Spartan3e (FPGA) by using Xilinx EDK tool.

Keywords: Discrete Wavelet Transform (DWT), FPGA, EDK, Micro Blaze, FSL Introduction

[1]. Z. Fan and R. D. Queiroz. Maximum likelihood estimation of JPEG quantization table in the identification of Bitmap Compression. IEEE, 948-951, 2000.

[2]. Charilaos Christopoulos, Athanassios Skodras, Touradj Ebrahimi,"The JPEG2000 still Image coding system: An overview". IEEE, 1103-1127, November 2000.

[3]. G. K. Wallace, "The JPEG Still Picture Compression Standard", IEEE Trans. Consumer Electronics, Vol. 38, No 1, Feb. 1992

[4]. W. B. Pennebaker and J. L. Mitcell, "JPEG: Still Image Data Compression Stndard", Van Nostrand Reinhold, 1993.

[5]. V. Bhaskaran and K. Konstantinides, "Image and Video Compression Standards:

[6]. ISO/IEC JTC1/SC29/WG1 N505, "Call for contributions for JPEG 2000 (JTC 1.29.14, 15444):Image Coding System," March 1997

[7]. ISO/IEC JTC1/SC29/WG1 N390R, "New work item: JPEG 2000 image coding system," March 1997.

[8]. M. Boliek, C. Christopoulos and E. Majani (editors), "JPEG2000 Part I Final Draft International Standard," (ISO/IEC FDIS15444-1), ISO/IEC JTC1/SC29/

[9]. T. Acharya and A. K. Ray, Image Processing: Principles and Applications. Hoboken, NJ: John Wiley & Sons, 2005

[10]. Alex Fukunaga and Andre Stechert, Evolving Nonlinear Predictive Models for Lossless Image Compression with Genetic Programming,