iosr-JVSP   Volume-1 ~ Issue-6

ABSTRACT: Conventional CMOS technology's performance deteriorates due to increased short channel effects. Double-gate (DG) FinFETs has better short channel effects performance compared to the conventional CMOS and stimulates technology scaling. The main drawback of using CMOS transistors are high power consumption and high leakage current. Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS in nano- scale circuits.FinFET, which is a double-gate field effect transistor (DGFET), is more versatile than traditional single-gate field effect transistors because it has two gates that can be controlled independently. Usually, the second gate of FinFET transistors is used to dynamically control the threshold voltage of the first gate in order to improve the performance and reduce leakage power. In this paper, we proposes a synchronous johnson counter by using FinFET Technology.FinFET logic implementation has significant advantages over static CMOS logic in terms of power consumption. The proposed counter was fabricated in 16nm FinFET technology in HSPICE.

Keywords – CMOS, Scaling, FinFET, Low Power Design, SET

[1] Anish Muttreja, Niket Agarwal and Niraj K. Jha,Dept. Of Electrical Engineering, Princeton University, Princeton, NJ 08544"CMOS Logic Design with Independent-gate FinFETs".

[2] Farhana Sheikh, Vidya Varadarajan, "The Impact of Device-Width Quantization on Digital Circuit Design Using FinFET Structures", EE 241 SPRING 2004.

[3] Michael C. Wang , "Independent Gate FinFET Circuit Design Methodology", IAENG International Journal of Computer Science, 37:1, IJCS_37_1_06.

[4] Varun P. Gopi and V. Sureshbabu,"Independently driven double gate FinFET scalable to 10nm" , 10th National Conference on Technological Trends (NCTT09) Nov2009.

[5] Nirmal,Vijaya kumar, Samjabaraj, Nirmal et al, ," Nand gate using finfet for nanoscale technology", International Journal of Engineering Science and Technology Vol. 2(5), 2010, 1351-1358".

[6] Imran Ahmed Khan,Mizra Tariq Beg,"Comparitive analysis of low power master slave single edge triggered flip flops",World applied sciences journal 16(special issue on recent trends on VLSI Design) 15-21,2012

[7] V Narendar,Wanjul Dattatray,R Sanjeev Rai,R. A.Mishra," Design of High-performance Digital Logic Circuits based on FinFET Technology", International Journal of Computer Applications (0975 – 8887) Volume 4,1– No.20, March 2012.

[8] Michael C. Wang, Low Power, Area Efficient FinFET Circuit Design, Proceedings of the World Congress of Engineering and Computer Science 2009 Vol I,WCECS 2009, October 20-22, 2009, San Francisco, USA.

[9] Sherif A.Tawfik, VolkanKursun, "FinFET domino logic with independent gate keepers", Microelectronics Journal.

[10] Vladimir Stojanovic,Vojin G.Oklobdzija,"Comparitive analysis of master-slave latches and flip flops for high performance and low power systems",IEEE Journal of Solid state circuits,vol 34,no.4,APRIL.

ABSTRACT: This paper presents low noise amplifier (LNA) for wireless application as RF front end which has been implemented in 0.13μ RF CMOS technology. The LNA was designed using inductive source degeneration cascode topology which produces better gain and good stability. From the simulation results, the LNA exhibits a gain of 26.46 dB, noise figure (NF) of 1.16 dB at 115μW , output return loss (S22) of −6.55dB, input return loss (S11) of −14.46dB, reverse isolation (S12) of −39.76 dB, and a power consumption is 7 mA from a 2.5V power supply.

Keywords - Low noise amplifier; RF front-end, cascode, CMOS, inductive source degeneration.

JOURNAL PAPERS:
[1] Brian A. Floyd, Jesal Mehta, Carlos Gamero, and Kenneth K. O, A 900-MHz, 0.8-pm CMOS Low Noise Amplifier with 1.2-dB Noise Figure, Silicon Microwave Integrated Circuits and Systems Research Group (SiMICS) Dept. of' Electrical and Computer Engineering, University of Florida, Gainesville.
[2] Andrew N. Karanicolas, A 2.7-V 900-MHz CMOS LNA and Mixer, Member, IEEE
[3] Arjuna Marzuki, GaAs pHEMT cascode LNA for wireless application, International journal of computer and electrical engineering ,vol.1,No.2,June 2009,1793-8163.
[4] Jon Guerber,Design of an 2.4GHz CMOS LNA, ECE 621,winter 2010.

ABSTRACT: Video Compression (VC) is one of the resource hungry key element in video communication and is commonly achieved using Motion Estimation (ME). In this paper we proposed power efficient one bit full adder and one of the simple and easy metric called Sum of Absolute Difference (SAD) for estimating the motion vectors in motion estimation. SAD is primarily used to detect motion in the video sub system. Here we proposed power efficient 4X4 and 8X8 SAD architectures. The proposed 4X4 SAD proves that 29%, 63.23% and 61.31% improvement in leakage power, dynamic power and total power respectively as compared with existing 4X4 SAD. Similarly the proposed 8X8 SAD which proves that 57%, 46.16% and 46.78% improvement in Leakage Power (LP), Dynamic Power (DP) and Total Power (TP) respectively as compared with that of existing 8X8 SAD at the gate level. The designs are implemented in ASIC methodology using cadence tools.

Keywords - SAD, ME, VC, CSA, DSP, LP, DP, TP, FPGA et

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