iosr-JVSP   Volume-16 ~ Issue-5 ~ Sep. - Oct. 2026

ABSTRACT: Approximate multiplication can reduce logic and switching activity in error-tolerant signal-processing and machine-learning hardware. This work presents a FPGA comparison of an 8-bit unsigned exact multiplier and an ordinary column-truncated multiplier in which partial products with i+j<CUT are omitted, with CUT=6. Both architectures are evaluated on an Avnet ZedBoard (XC7Z020-CLG484-1) using Xilinx Vivado 2019.2 with common timing constraints, and synthesis with DSP inference disabled. Post-route measurements are reported over target clock frequencies from 100 to 190 MHz for both architectures, with an additional 200-MHz point for the truncated......

Keywords - approximate computing, FPGA, truncated multiplier, partial-product truncation, dynamic power, power-delay product, area-delay product.

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ABSTRACT: With growing demand for bio medical electronics, healthcare monitoring and AI integrated bio medical applications, bio medical sensor and signal processing has become a vital part of the industry. The most important part of the biomedical electronics is to interface the sensor with the nervous system of the subject, sense the neuro transmitted signal, amplify the signal to machine readable amplitude, sample the signal, convert it to digital for and perform DSP. Instrumentation amplifiers are the crucial part of these biomedical sensors not only in terms of EEG, ECG and other lifesaving technologies but also in brain signal detection and modification. This paper talks about the crucial intermediate step of amplification of sensed neural transmitted signals to the level that can be read by Sampling circuits and ADCs.

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ABSTRACT: The research explores various hardware acceleration approaches, beginning with Graphics Processing Units (GPUs) that leverage their massively parallel architecture to accelerate matrix operations fundamental to neural networks. We examine the architectural advantages of GPUs, including their thousands of cores optimized for floating-point operations, high memory bandwidth, and specialized tensor processing units. The analysis extends to Application-Specific Integrated Circuits (ASICs) such as Google's Tensor Processing Units (TPUs), which....

Key Terms—FPGA; energy-aware design; CNN accelerator; SVM accelerator; memory hierarchy; dataflow; quantization ;CNN; FPGAs; GPUs; ML Workloads; SVM.

[1] A. G. Blaiech, K. Ben Khalifa, C. Valderrama, M. A. C. Fernandes, and M. H. Bedoui, “A survey and taxonomy of FPGA-based deep learning accelerators,” Journal of Systems Architecture, vol. S. Mittal, “A survey of FPGA-based accelerators for convolutional neural networks,” Neural 98, pp. 331–345, 2019, doi: 10.1016/j.sysarc.2019.01.007.
[2] Computing and Applications, vol. 32, pp. 1109–1139, 2020, doi: 10.1007/s00521-018-3761-1.
[3] S. I. Venieris, A. Kouris, and C.-S. Bouganis, “Toolflows for mapping convolutional neural networks on FPGAs: A survey and future directions,” ACM Computing Surveys, vol. 51, no. 3, Art. no. 56, pp. 1–39, 2018, doi: 10.1145/3186332.
[4] C. Zhang, P. Li, G. Sun, Y. Guan, B. Xiao, and J. Cong, “Optimizing FPGA-based accelerator design for deep convolutional neural networks,” in Proc. ACM/SIGDA Int. Symp. Field-Programmable Gate Arrays (FPGA), 2015, pp. 161–170, doi: 10.1145/2684746.2689060.
[5] Y.-H. Chen, T. Krishna, J. S. Emer, and V. Sze, “Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks,” IEEE Journal of Solid-State Circuits, vol. 52, no. 1, pp. 127–138, 2017, doi: 10.1109/JSSC.2016.2616357.

ABSTRACT: Accidents at railway level crossings are still a major safety concern, especially at un-manned level crossings where the manual operation of the gates is prone to delays and human error. In this research, an automated railway gate control system has been designed using VLSI technology and Verilog hardware description language (HDL) to improve the safety and efficiency of railway operation. The proposed system uses infrared sensors to detect arrival and departure....

Key Terms—Automatic Railway Gate Control, VLSI Technology, Verilog HDL, FPGA Implementation, Railway Safety Automation

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