iosr-JVSP   Volume-11 ~ Issue-3 ~ May - Jun. 2021

ABSTRACT: This work presents the functionality of some unique Schmitt trigger circuits designed on the basis of the impact of load capacitance and supply voltages together with hysteresis width, propagation delay and average power dissipation. All the simulation results are performed for 0.18 μm CMOS process technology. It is found that through the recommended design a larger hysteresis width can be attained by modifying the arrangement and organization of transistors as well as the ratio of width to length of channel. The results of our analysis reveal that the designed Schmitt trigger can be driven using low voltage of 0.8-1.5 V and the power dissipation is reduced to only 47.24 pW. The total active area of our suggested trigger circuit is 10.80 × 10.65 μm2. The proposed Schmitt trigger will be suitable and useful where large hysteresis width is required to improve the noise margin. Therefore, it may be propounded that our designed Schmitt trigger have low power dissipation, large hysteresis width and plausibly be operated with lower voltage compared to earlier designs found in literature.

Key Words: Schmitt trigger; Hysteresis width; Power dissipation; Propagation delay

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ABSTRACT: In today's high performance advanced VLSI circuit design including most semicustom design gives efficient utilization of circuit resources with better productivity offering a good layout density and high performances with optimum resources in submicron designs. The main idea is to divide the processor into small partitions called Functional Unit Block (FUB) based on the different functionalities of the processor like Execution, Memory, Fetch, Decode and Out of order. The major focus of this work is to optimize the FUB in terms of timing, power and area. With the enhancement of the existing design technology and optimization methods, new design technology called datapath design is used to deliver a quality design and this work also proposes various logical optimization.....

Key Words: datapath;synthesis;optimization;timing;clock tuning;

[1]. Linumon Thomas and Kiran V, "Timing Convergence Techniques in Digital VLSI Designs"
[2]. Mohamed Khalil Hani and Nasir Shaikh-Husin, "Simultaneous Routing and Buffer Insertion Algorithm for Interconnect Delay
Optimization in VLSI Layout Design"
[3]. Narendra Shenoy, Mahesh Iyer, Robert Damiano, Kevin Harer and Hi-Keung Ma ,"A Robust Solution to the Timing Convergence
Problem in High-Performance Design," ACM Transactions on Design Automation of Electronic Systems, vol. 11, no. 2, pp. 306-
324, April 2006
[4]. http://www.intelpedia.intel.com

ABSTRACT: Half-unit-biased (HUB) is a new design that is based on the displacement of the digits represented by half the unit last performed. This arrangement makes the two's complement and round operations closest by avoiding any carry propagation. This saves energy, time and area consumption. Given that the IEEE floating point standard uses unbiased rounding as the default mode, this feature is also desirable for HUB approaches. In this article, we study unbiased rounding for HUB floating point addition both within independent operation and within FMA. We show two different options to eliminate bias by eliminating the sum results either partially or completely. Implementation results of the proposed architecture to help designers decide what their best option.

Keywords: HUB format, unbiased rounding, Floating point , IEEE

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