iosr-JVSP   Volume-5 ~ Issue-5 ~ Sep-Oct 2015

ABSTRACT: The most area and power consuming arithmetic operation in high-performance circuits like Finite Impulse Response (FIR), multiplication is one. There are different types of multipliers to reducing the cost and effective parameters in FIR filter design. Among those this paper use truncated multiplier and modified Wallace multiplier in the FIR design. The structural adders and delay elements occupies more area and consumes power in this form so it was a reason to forward the proposed method. In prior FIR filters design with low cost effective results will done by the faithfully rounded truncated multipliers with the carry save additions. In MCMAT design the low cost FIR filters within the best area and power results are implement in this paper by using the improved truncated methods.

[1]. Shen-Fu Hsiao, Jun-Hong Zhang Jian, and Ming-Chih Chen,‖Low-Cost FIR Filter Designs Based on FaithfullyRounded Truncated Multiple ConstantMultiplication/Accumulation‖ieee transactions on circuits and systems—ii: express briefs, vol. 60, no. 5, may 2013.
[2]. M. M. Peiro, E. I. Boemo, and L. Wanhammar, ―Design of high-speedmultiplierless filters using a nonrecursive signed common subexpression algorithm,‖ IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process.,vol. 49, no. 3, pp. 196–203, Mar. 2002.
[3]. C.-H. Chang, J. Chen, and A. P. Vinod, ―Information theoretic approachto complexity reduction of FIR filter design,‖ IEEE Trans. Circuits Syst.I, Reg. Papers, vol. 55, no. 8, pp. 2310–2321, Sep. 2008.
[4]. F. Xu, C. H. Chang, and C. C. Jong, ―Contention resolution—A newapproach to versatile subexpressions sharing in multiple constant multiplications,‖IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 2,pp. 559–571, Mar. 2008.

ABSTRACT: Low-Noise Amplifier (LNA), with a broadband circuit appears attractive because of the reduced cost realized by area reduction due to replacing of resistor with switch capacitor. The demand for a low-cost but high performance wireless front-end, many intensive researches on CMOS radio-frequency (RF) front-end circuit has been carried out. The goal is to minimize the cost and enhance the performance, low power consumption design. To design a Low Noise Amplifier one of the method which we have used is an inductor-less noise cancelling broadband using switch capacitor with composite transistor pair. The composite pair of NMOS/PMOS cross coupled transistor is used to amplify the input signal while reducing noise figure. It reduces the noise figure by partially cancelling noise which is generated by the input transistor pair.

[1] M. Zargari,M. Terrovitis, S. H.-M. Jen, B. J. Kaczynski,M. P.MeeLan Lee Mack, et.al. "A single-chip dual-band tri-mode CMOS transceiver for IEEE 802. 11a/b/g wireless LAN," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2239–2248, Dec. 2004.

[2] J. Ko, J. Kim, S. Cho, and K. Lee, "A 19-mW 2.6-mm L1/L2 dualband CMOS GPS receiver," IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1414–1425, Jul. 2005.

[3] K. Muhammad, H. Yo-Chuol, T. L. Mayhugh, H. Chih-Ming, T. Jung, I. Elahi, C. Lin, I. Deng, C. Fernando, J. L. Wallberg, S. K. Vemulapalli. Larson, T. Murphy, D. Leipold, P. Cruise, J. Jaehnig, M.-C. Lee, R. Staszewski, R. Staszewski, and K. Maggio, "The first fully integrated quad-band GSM/GPRS receiver in a 90-nm digital CMOS process," IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1772–1783, Aug. 2006.

[4] F. Bruccoleri,E. A. M. Klumperink, and B. Nauta, "Wide-band CMOS low-noise amplifier exploiting thermal noise cancellation," IEEE J. Solid-State Circuits, vol. 39, no. 2, pp. 275–282, Feb. 2004.

[5] J.-H. C. Zhan and S. S. Taylor, "An inductor-less broadband LNA with gain step," in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC), 2006, pp. 344–347.