iosr-JVSP   Volume-4 ~ Issue-6 ~ Nov-Dec 2014

ABSTRACT: Low Power design is main object in the Very Large Scale Integration (VLSI) Design Gate Diffusion Input (GDI): a new technique for designing the low power digital circuits. This technique allows reducing the power consumption, propagation delay and area of digital circuits. In this paper, a Full Swing Gate Diffusion Input (FS-GDI) methodology is proposed for designing the low power digital circuits. This proposed technique is applied to a 180 nm technology with 1v supply voltage carry look ahead adder (CLA) using MENTOR GRAPHICS.

Keywords: Pass Transistor Logic, Transmission Gate, GDI, Full Swing GDI, Power Dissipation, Delay.

[1]. N. Weste and K. Eshraghian, principles of CMOS digital design. Reading, MA: Addison-Wesley, pp.304-307.
[2]. A.P. Chandrakasan and R.W. Brodersen, "Minimizing Power Consumption in digital CMOS circuits," Proc. IEEE J. Solid –State circuits, vol.83, pp. 498-523, Apr.1995.
[3]. Arkadiy Morgenshtein, Alexander Fish, and Israel A. Wagner, "Gate Diffusion Input (GDI): A power efficient method for combinational circuits", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol,10, NO. 5, October 2002.
[4]. A.P. Chandrakasan and, S.Sheng, and R.W. Brodersen "Low Power CMOS digital Design," Proc. IEEE J. Solid –State circuits, vol.27, pp. 473-484, Apr.1992.
[5]. W. Al-Assadi, A.P. Jayasumana, and Y.K.Malaiya, " Pass Transistor logic design," Int. J. Electron, vol.70,pp.739-749,1991
[6]. R. Zimmermann and W. Fichtner," low-power logic styles: CMOS versus Pass Transistor Logic ," IEEE J. Solid –State circuits, vol.32, pp. 1079-1090, Jun-1997.

ABSTRACT: Security or the lack of it has become a world topical issue today. It is no more news that with the fast increase in technological innovations, sophistication and rise in crime has also become an issue. This has led to an increased demand for better and more secure ways to protect that which we hold precious. This paper adopted the Structure Systems Analysis and Design Methodology (SSADM) and prototyping with the aims of addressing the security issues. At the same time, it attempts to create a microcontroller controlled pass-worded security door embedded with alarm. The system is expected to go off and alert security personnel whenever a wrong password is inputted for three consecutive times. Based on the structural specifications, if dully implemented, would greatly improve the security condition obtainable.
Keywords: Practical prototyping, microcontroller, technological innovations and password.

[1]. Augarten, Stan (1983). The Most Widely Used Computer on a Chip: The TMS 1000. New Havenand New York: Ticknor &
Fields. pp. 5. ISBN 0-89919-195-9.
[2]. Beck, Leland L. (1996). "2". System Software: An Introduction to Systems Programming. Addison Wesley

[3]. Buah FK (1969). The Ancient World, A new History for Schools and Colleges. Book 1, 2nd Edition. London and Basingstoke:
Macmillian Education Limited.
[4]. Dorf, Richard C.; Svoboda, James A. (2001). Introduction to Electric Circuits (5th ed.), pp. 64-65. New York: John Wiley and Sons,
Inc.. ISBN 0-471-38689-8.
[5]. Federal Financial Institutions Examination Council (2008). "Authentication in an Internet Banking Environment". Retrieved 2012-
07-24.

ABSTRACT:In every research effort, the first issue is to define the research problem properly, that is, the problem to be investigated or solved. The next issue is to select the research design. The research design occupies a very< critical point in research since the success of the entire research work depends largely on the research design. It is the structure and planning of the entire approach to a problem for research. Research design answers some crucial questions such as "how was the data collected or generated, and how was it analyzed" In other words, it shows your reader how you obtained your result and why in this study surve research design and case study research designs are discussed.

[1]. Holsti, Ole R. (1996). Content analysis for the social sciences and Humanities (massachussets: Additional wesly publishing
company).
[2]. Ikeagwu, E. K. (1998). Groundwork of research: methods and procedures. (Enugu: Institute of development studies University of
nigeria, enugu campus.
[3]. Leedy, Paul D. (1980). Practical Research: planning and design (new york: macmillan publishing company, inc.)
[4]. Oppenhein, A. N. (1970). Questionnaire design and Attitude measurement (london: Heinemann educational books ltd.)
[5]. palmquist, mike(2005). Survey Research. Colorado state university, department of english.
(Http//writing.colostate.edu/guides/research/survey/).

ABSTRACT: Leakage current has become a regime in deep sub micrometer circuits. When we move from one technology generation to another technology generation leakage current component is increasing. Out of the total power dissipation majority is the leakage power. The dominant component of leakage power is sub threshold leakage current. Minimizing leakage current is very important in battery powered applications since the leakage drains the battery when circuit is idle. In this paper a survey is done in such a manner so as to outline what so far has done to reduce the leakage power. The paper is organized in such manner that it gives a brief description about standby leakage mechanisms, various standby leakage reduction techniques and what all are the existing technique's available.

Keywords: Leakage current, Standby leakage, Transistor stack, IVC, PBS, SAT solver

[1]. K. Roy, S. Mukhopadhaya, and H. Mahmoodi- Meimand, "Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits," Proc. IEEE, vol. 91, no. 2, Feb. 2003, pp. 305-327
[2]. A model for leakage control by MOS transistlor stacking Mark C. Johnson Purdue University School of Electrical and Computer Engineering ,DineshSomasekhar Purdue University School of Electrical and Computer Engineering KaushikRoy,Purdue University School of Electrical and Computer Engineering.
[3]. S. Bobba and I. Hajj, "Maximum Leakage Power Estimation for CMOS Circuits," in Proc. of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design, 1999.
[4]. Z. Chen, M. Johnson, L. Wei, and K. Roy, "Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks," in Proc. ISLPED, 1998, pp. 239–244.
[5]. J. Halter and F. Najm, "A gate-level leakage power reduction method for ultra-low-power CMOS circuits," in Proc. of the IEEE 1997 Custom Integrated Circuits Conference, 475-478, 1997.