Version-1 (July-August 2014)
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| Paper Type | : | Research Paper |
| Title | : | Advancements in Gesture Recognition Technology |
| Country | : | India |
| Authors | : | Poluka Srilatha, Tiruveedhula Saranya |
| : | 10.9790/4200-04410107 ![]() |
Keywords: Algorithm, AllSee, GUI, HMI, sign language
[1]. http://en.wikipedia.org/wiki/Facial_recognition_system
[2]. http://en.wikipedia.org/wiki/Gesture_recognition
[3]. https://goldin-meadow-lab.uchicago.edu/sites/goldin-meadow lab.uchicago.edu/files/uploads/PDFs/1999_GM.pdf
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ABSTRACT: This paper presents a novel method for detecting cardiac abnormalities in a way which is both non- invasive and low cost. This method utilizes the presence of harmonics generated within the human heart as indicators of possible cardiac abnormalities such as cardiac blocks or cardiac valve dysfunctions. Our work is divided into two sections; firstly, the establishment of the fundamental frequency of the human heart along with its associated sub-harmonics and secondly, the presence of various harmonics in normal and abnormal cardiac signals which may serve as possible indicators to determine cardiac dysfunctions. Our method was applied on Phonocardiograph (PCG) signals of patients with various cardiac conditions.
Keywords: Curve Fitting, Fourier Series, Frequency Spectrum, Harmonics, Phonocardiogram
[1] Howard B. Sprague, M.D., Patrick A. Ongley, M.D., "The Clinical Value of Phonocardiography", Circulation. 1954;9:127-134
[2] Sandra LachArlinghaus, PHB Practical Handbook of Curve Fitting. CRC Press, 1994.
[3] William M. Kolb. Curve Fitting for Programmable Calculators. Syntec, Incorporated, 1984
[4] C. Chatfield (1989). The Analysis of Time Series—An Introduction (fourth ed.). Chapman and Hall, London. pp. 94–95. ISBN 0-412-
31820-2.
[5] Hannan, E.J., "Stationary Time Series", in: John Eatwell, Murray Milgate, and Peter Newman, editors, The New Palgrave: A
Dictionary of Economics. Time Series and Statistics, Macmillan, London, 1990, p. 271.
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ABSTRACT: In this paper, we tend to take four domino circuit topologies to boost the strength and lower the consumption of power. A high speed and noise immune domino logic circuit is given that uses the property of the footer semiconductor to raise the sensitivity of the dynamic node to noise and eventually in improved performance. Dynamic logic circuits are used for prime performance and high speed applications. We tend to analyze and compare completely different domino logic style topologies for lowering the sub-threshold outpouring current in standby mode NMOS block , increasing the speed and increasing the noise immunity. We tend to compare power, delay, and Power Delay Product (PDP) of various topologies. Simulation is finished employing a 45nm cadence tool for eight input OR circuit. Our projected circuits scale back power consumption by 100 percent to 35 the troubles, improvement of unity noise gain of 39% to 85% and have a higher figure of advantage as compared to conditional keeper domino. The simulation results unconcealed that prime Speed Conditional keeper Domino (CKD) circuit offers the most effective ends up in terms of reduction in delay and power consumption as compared to different circuits.
Key words: CMOS, domino logic, keeper ratio, Standby power, Noise immunity, Lower power design
[1]. Roy, K., S. Mukhopadhyay and H. Mahmoodi, 2002. Leakage curreent in deep-submicron CMOS circuits, Journal of Circuits, Syst. Comput, 11(6): 575-600.
[2]. De, V. and S. Borkar, 1999. Technology and design challenges for low power and high performance, in Proc. Int. Symp. Low Power Electronics and Design, pp: 163-168.
[3]. Anders, M., R. Krishnamurthy, R. Spotten and K. Soumyanath, 2001. Robustness of sub-70nm dynamic circuits:Analytical techniques and scaling trends, in Proc.Symp. VLSI Circuit, pp: 23-24.
[4]. Wairya, S., R.K. Nagaria and S. Tiwari, 2012. Performance analysis of high speed hybrid CMOS full adder circuits for low voltage VLSI design, full adder circuits for low voltage VLSI design.
[5]. Kao, J.T. and A.P. Chandrakasan, 2000. Dual- threshold voltage techniques for low power digital circuits, IEEE Journal of Soloid-State Circuits, 35(7): 1009-1018.
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| Paper Type | : | Research Paper |
| Title | : | Design and Characterization of Third Generation Current Conveyor |
| Country | : | India |
| Authors | : | Payal shah, Amisha Naik |
| : | 10.9790/4200-04412328 ![]() |
ABSTRACT: This paper presents a low power low voltage positive third generation current conveyor using four simple first generation current conveyors. It is designed and simulated in a standard 0.18um TSMC 1P, 6M CMOS process. This current conveyor design with the help of design architect and IC station (mentor graphics). Its DC, AC and transient analysis is carried out with ELDO tool. Its pre layout and post layout results are also given.
Keywords: Current mode circuit, third generation current conveyor
[1]. FABRE, A.: "Third-generation current conveyor: A new helpful active element‟, Electron. Lett.. 1995, 31, (9, pp. 338-339
[2]. BRUUN, E.: "Class AB CMOS first-generation current conveyor‟, Electron. Lett.. 1995, 31, (6), pp. 422423
[3]. A. Piovaccari, "CMOS integrated third-generation conveyor," Electronics Letters, Vol. 31, No. 15, pp. 1228-1229, 1995.
[4]. Giuseppe Ferri and Nicola C. Guerrini."Low Voltage Low Power CMOS Current Conveyors"by Pg no.126-128
[5]. Kimmo Koli,,''CMOS Current Amplifiers:Speed versus Nonlinearity",Ph.D,Dissertation,Helsinki University of Technology,Finalnd,Oct-2000.
