iosr-JVSP   Volume-3 ~ Issue-2

ABSTRACT:The most important issues in video watermarking are invisibility of the watermark and the resilience of watermarking to attacks. The area of video watermarking has focused primarily on the problem of robustness to geometric attacks, while discounting the problem of more sophisticated attackers. So to improve the robustness of watermark for A new digital watermarking algorithm, for based on LDPC coding ,to embedded the watermark in videos that insert information in the side view, unlike the regular approaches that insert on the frames. Video watermarking technology has applied image watermarking technology to individual frames of a video. The implemented watermarking system operates in the spectrum domain where a subset of the discrete wavelet transform (DWT) coefficients is modified by the watermark without using the original image during watermark extraction. The quality of watermark is evaluated by taking into account the trade-off between the chip-rate and the rate of LDPC codes.

Keywords: Digital Video watermarking, LDPCEncoder and LDPC Decoder, Robust watermarking, DWT

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ABSTRACT: Monte Carlo based SSTA serves as the golden standard against the alternative SSTA algorithms. The efficient implementation of MC-SSTA is performed by repeatedly executing ordinary STA using a set of randomly generated delay samples. The FPGA device is used as a target device onto which the RTL description is mapped, which acts as a dedicated STA engine. We leverage the path level and gate level parallelisms and the power optimizations of normal distribution random number generators based on central limit theorem. The accuracy is compared with the Mersenne Twister and Box Muller Methods which are high quality random number generators.

Keywords: FPGA, Linear feedback shift register, Monte Carlo, SSTA.

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ABSTRACT: The uninterrupted development of memory market has experienced a new face since the beginning of the 21st century due to the emergence of pc markets such as Laptop, Server PC, Tablet and Smart phones. This paper demonstrates the implementation of intelligent high performance memory access technique of DDR3 SDRAM. This paper discusses the full architecture of DDR3 SDRAM controller with minimum accessible time. It is designed to achieve high performance memory access with faster read and write. Keywords - Architecture of DDR3 controller, DDR3, High geared access, RAM Controller, SDRAM

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