iosr-JVSP   Volume-2 ~ Issue-3

ABSTRACT: At present, the importance of improving a traffic system has become more important than ever before due to the immense number of vehicles on the road. In this paper a unifying philosophy for carrying out different level of image processing has been presented in order to find the best possible outcomes to solve the vision problem at night time. The whole process was done using the low level and mid level image processing algorithms. As there is no fixed method of doing this kind of transformations, in this paper different types of transformations have used to find out the best possible output. There are different types of edge detection techniques in order to detect the substances properly. In case of segmentation, there are different algorithms which can be manipulated according to the purpose. Here we have used some of these techniques to find out the best possible method for this job. Merging with logarithmic and power law transformation this edge detection and segmentation technique produces the output that we have longed for.

Keyword – Image and Video processing, Image Enhancement, Gray Level Transformation, Image Segmentation.

[1] http://www.who.int/violence_injury_prevention/publications/road_traffic/world_report/en/index.html
[2] Bolen J et al. Overview of efforts to prevent motor vehicle-related injury. In: Bolen J, Sleet DA, Johnson V, eds. Prevention of motor vehicle-related injuries: a compendium of articles from the Morbidity and Mortality Weekly Report, 1985–1996. Atlanta, GA, Centers for Disease Control and Prevention, 1997..
[3] http://www.wisegeek.com/what-is-video-processing.htm
[4] Jones, W. ,Keeping cars from crashing, IEEE Spectrum, Vol. 38, No. 9, pp. 40-45. (2001):
[5] Rafael C. Gonzalez, Richard E. Woods ,Digital image processing Second Edition .
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[8] Oge Marques, Practical Image and Video Processing using Matlab,.
[9] Birkhauser, Boston , Jean-Michel Morel and Sergio Solimini ,Variational methods in Image Segmentation , Progress in Nonlinear Differential Equations and Their Applications, Vol 14.
[10] POLAK, M., ZHANG, H. & PI, M.,An evaluation metric for image segmentation of multiple objects. Image and Vision Computing, 27(8):1223-1227. 2009.

ABSTRACT: Leakage power has become an important contributing factor of power for the CMOS circuits in deep sub-micron process. MTCMOS is a very effective technique to reduce the leakage current of circuits in the standby mode. Placing a global sleep device is not practical and sleep device at fine grain level involves more number of sleep transistors and more routing space. Distributed MTCMOS is better technique with self sleep circuit to avoid complexities in routing and sleep distribution network. A simple FFT processor is designed with self sleep buffer using body bias to reduce its standby power. Ccomparisons are made between leakage power for FFT implemented in CMOS and distributed self sleep FFT using the 90nm CMOS technology in cadence tools.

Keywords – FFT, Leakage power, MTCMOS, Sleep device, Standby mode.

[1] Archana Nagda, et.el " Leakage Power Reduction Techniques: A New Approach", International Journal of Engineering Research and Applications, Vol. 2, Issue 2,Mar-Apr 2012, pp.308-312.

[2] C. Long, and L. He, "Distributed sleep transistor network for power reduction," IEEE Trans. VLSI Syst., vol. 12, no. 9,Sep. 2004. [3] K. Shi, D. Howard, "Sleep transistor design and implementation – simple concepts yet challenges to be optimum," in Proc. Int. Symp. VLSI Design, Automation and Test, pp. 1-4, April 2006.

[4] V. Khandelwal and A. Srivastava, "Leakage control through fine-grained placement and sizing of sleep transistors," in Proc. EEE/ACM Int. Conference on CAD, pp. 533-536, 2004.

[5] B. H. Calhoun, F. A. Honore, and A. P. Chandrakasan, "A leakage reduction methodology for distributed MTCMOS," Jour.Solid-State Circuits, vol. 39, no. 5, pp. 818-826, May 2004..

[6] P. Saxena, N. Menezes, P. Cocchini, D. A. Kirkpatrick, "Repeater scaling and its impact on CAD," IEEE Trans. CAD of Integ. Circuits and Syst., vol. 23, no. 4, pp. 451-463, Apr. 2004.

[7] Charbel J. Akl and Magdy A. Bayoumi "Self-Sleep Buffer for Distributed MTCMOS Design" 21st International Conference on VLSI Design, the Center for Advanced Computer Studies (CACS).

[8] T. Esther Rani and Dr. Rameshwara rao,"Design of simple general purpose microprocessor with self sleep buffer", International Journal of Computer Applications, Vol66-No20, March 2013.
[9] www.cmlab.csie.ntu.edu.tw/cml/dsp/training/coding/transform/fft.html

ABSTRACT: In this paper we have analyzed the advantages of using dynamic circuits over static circuits with result oriented example for NAND operation. The different aspects covered under this discussion include power, speed, area, input Capacitance and timing delays calculation. We have also covered the problem of increase in dynamic power dissipation at the dynamic and the output node in dynamic circuits. A circuit is proposed for un-footed dynamic buffer circuit where the power dissipation is reduced from 256μW to 142μW at the output node in the proposed circuit as compared to that in standard dynamic domino logic buffer circuit. Simulation results are obtained using 0.12μm CMOS technology.

Keywords - Dynamic Circuits, Domino Logic, Keeper Circuit, Buffer, Power Dissipation, Skewed Gates

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[2] Amit Kumar Pandey, Ram Awadh Mishra, Rajendera Kumar Nagaria, "Low Power Dynamic Buffer Circuits," International Journal of VLSI design and Communication Systems(VLSICS), Vol 3, No. 5, October, 2012.
[3] A. K. Pandey, R. A. Mishra, R. K. Nagaria, "Static Switching Dynamic Buffer Circuit,".
[4] Volkan Kursun, Eby G. Friedman, "Speed and Noise Immunity Enhanced Low Power Dynamic Circuits," Name of Journal/ Conference/ Book, Vol x, No. x, pp. x-x, Year.
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[6] S. Wairya, R. K. Nagaria and S. Tiwari, "Comparative performance analysis of XOR-XNOR function based high speed CMOS full adder circuits for low voltage VLSI design",International Journal of VLSI design and Communication Systems (VLSICS), AIRCC Publication, vol.3, no. 2,pp.221-242, 2012.
[7] Y. J. Ren. ,I. Karlsson and Svensson, "A true single-phase clock dynamic CMOS circuit technique",IEEE Transactions on Solid-State Circuits,vol no. 22,pp.899-901,1987.