iosr-JVSP   Volume-2 ~ Issue-1

ABSTRACT: MOS is an old transistor technology that provides low power consumption, but has a shorter channel for the flow of current and thereby has some drawbacks like excessive current usage and larger size. The FinFET (Fin Field Effective Transistor) is an upcoming technology has a longer channel gate. The size ranges from 32nm, 22nm by Intel and finally it has been shrunk to 14nm by Samsung. This project is a study of these two technologies and we are able to distinguish the techniques and make CMOS as worth as FinFET.

Keywords : CMOS,FinFET,Samsung,Fin

[1] R. Chau, J. Kavalieros, B. Roberds, R. Schenker, D. Lionberger, D. Barlage, B. Doyle, R. Arghavani, A. Murthy, and G. Dewey, "30 nm physical gate length cmos transistors with 1.0 ps n-mos and 1.7 ps p-mos gate delays," in Electron Devices Meeting, 2000. IEDM'00. Technical Digest. International. 1em plus 0.5em minus 0.4em IEEE, 2000, pp. 45–48.
[2] T. Poiroux, M. Vinet, O. Faynot, J. Widiez, J. Lolivier, T. Ernst, B. Previtali, and S. Deleonibus, "Multiple gate devices: advantages and challenges," Microelectronic Engineering, vol. 80, pp. 378–385, 2005.
[3] F. Rossem, "Doping extraction in finfets," 2009.
[4] F. van Rossem, "Doping extraction in finfets," 2009.
[5] B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King et al., "Finfet scaling to 10 nm gate length," in Electron Devices Meeting, 2002. IEDM'02. International. 1em plus 0.5em minus 0.4em IEEE, 2002, pp. 251–254.

ABSTRACT: TCyclic Redundancy Check is an established technique for detecting errors on serial data communication links and in mass storage devices. A frame check sequence is appended to the message for transmission error detection in Many (high-speed) serial data communication protocols. The common hardware solution for CRC calculation is the linear feedback shift register (LFSR), consisting a few Flip Flops and Logic Gates. CRC is the preferred and most efficient method used for detecting bit errors produced from medium related noise. Data storage is another area where CRC error detection is becoming increasingly important. CRC checks to be executed at high speed as well as parallel processing. The ability of CRC implemented in hardware to be reconfigurable to handle new Generator polynomials will offer a key advantage in this fast developing area. The reconfigurable CRC circuit that has been implemented can quickly switch between any polynomial gives it a key advantage over the other circuits. In this paper it is proposed

Keywords - CRC (cyclic Redundancy check) ,FEC(Forward Error correction), Generator polynomial, LFSR(Linear feed back Shift Register), Reconfigurable circuit

[1] Data Communications and Networking , Third Edition By Behrouz A.Forouzan.

[2] P. Koopman and T. Charkravarty, "Cyclic Redundancy Code (CRC) polynomial selection for embedded networks," in Proc. DSN, pp. 145–154.

[3] Design and Implementation of a Field Programmable CRC Circuit Architecture, Ciaran Toal, Kieran cLaughlin, Sakir Sezer, and Xin Yang

[3] P. Koopman, "32-bit cyclic redundancy codes for internet applications," in Proc. DSN, pp. 459–472.640–651, Dec. 1995.

[5] T. Bi-Pei and C. Zukowski, "High-speed parallel CRC circuits in VLSI," IEEE Trans. Commun., vol. 40, no. 4, pp. 653–657, Apr. 1992.

[6] J. H. Derby, "High-speed CRC computation using state-space transformations," in Proc. Globecom, Nov. 2001, pp. 166–170.

[7] M.-D. Shieh, M.-H. Sheu, C.-H. Chen, and H.-F. Lo, "A systematic approach for parallel CRC computations," J. Inf. Sci. Eng., vol. 17, pp.445–461, 2001.

[8] T. Henriksson and D. Liu, "Implementation of fast CRC calculation," in Proc. ASP-DAC, 2003, pp. 563–564.

[9] F. Monteiro, A. Dandache, A. M‟sir, and B. Lepley, "A fast CRC implementation on FPGA using a pipelined architecture for the polynomial division," in Proc. ICECS, 2001, vol. 3, pp. 1231–1234.

[10] O. Weiss, M. Gansen, and T. Noll, "A flexible data path generator for physical oriented design," in Proc. ESSCIRC, Villach, Sep. 2001, pp. 408–411.

ABSTRACT: In modern Trends, the demand for memory has been increases tremendously. The reduction in SRAM operating voltage, cell stability and the increase in process variation with process scaling are the main concerns and can be done by Schmitt-Trigger Techniques. Read and write assist techniques are now commonly used to lower the minimum operating voltage (Vmin) of an SRAM. This paper presents a proposed 7T, 8T SRAM cell based on a various read and write assist technique and reduces the total power consumption and not area overhead of SRAMs while maintaining their performance and compare the output power. Simulation results with 180nm, 120nm CMOS technology.

Keywords - Low-Voltage SRAM, Process Tolerance, Schmitt-Trigger (ST), Vmin.

[1] Jaydeep P. Kulkarni. Kaushik Roy.: ―Ultralow-Voltage Process-Variation Tolerant Schmitt- Trigger-Based SRAM Design‖, IEEE Transaction on Very Large Scale Integration (VLSI) Systems, Vol.20, NO.2, Febraury 2012.

[2] K. Takeda, Y. Hagihara, Y. Aimoto, M. Nomura, Y. Nakazawa, T. Ishii, and H. Kobatake, ―A read-static-noise-margin-free SRAM cell for low-Vdd and high-speed applications,‖ in Proc. Int. Solid State Circuits Conf., Feb. 2005, pp. 478–479.

[3] N. Verma and A. P. Chandrakasan, ―65 nm 8T sub-Vt SRAM employing sense-amplifier redundancy,‖ in Proc. Int. Solid State Circuits Conf., Feb. 2007, pp. 328–329.

[4] V. Ramadurai, R. Joshi, and R. Kanj, ―A disturb decoupled column select 8T SRAM cell,‖ in Proc. Custom Integr. Circuits Conf., Sep. 2007, pp. 25–28.

[5] Y. Morita, H. Fujiwara, H. Noguchi, Y. Iguchi, K. Nii, H. Kawaguchi, and M. Yoshimoto, ―An area-conscious low-voltage-oriented 8T-SRAM design under DVS environment,‖ in Proc. VLSI Circuit Symp., Jun. 2007, pp. 14–16.

[6] M. Grossar, M. Stucchi, K. Maex and W. Dehaene, ―Read Stability and Write-ability analysis of SRAM Cells for Nanometer Technologies‖, IEEE J. Solid State Circuits, vol.41, no. 11, pp. 2577-2588, Nov. 2006.

[7] Z. Liu and V. Kursun, ―High read stability and low leakage cache memory cell,‖ IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 4, pp. 488–492, Apr. 2008.

[8] S. Lin, Y.-B. Kim, and F. Lombardi, ―A highly-stable nanometer memory for low-power design,‖ in Proc. IEEE Int. Workshop Design Test of Nano Devices, Circuits Syst., 2008, pp. 17–20.

[9] J. P. Kulkarni, K. Kim, and K. Roy, ―A 160 mV robust Schmitt trigger based subthreshold SRAM,‖ IEEE J. Solid-State Circuits, vol. 42, no.10, pp. 2303–2313, Oct. 2007.

[10] J. P. Kulkarni, K. Kim, S. Park, and K. Roy, ―Process variation tolerant SRAM array for ultra low voltage applications,‖ in Proc. Design Autom. Conf. , Jun. 2008, pp. 108–113.