iosr-JVSP   Volume-11 ~ Issue-5 ~ Sep. - Oct. 2021

ABSTRACT: In Very Large Scale Integration (VLSI) technology, the main objective is to shrink the area and thereby to raise the packing density for performance improvement in terms of power consumption, noise, delay, operating frequency, etc. A carry look-ahead adder circuit is an important block in any digital circuit. It improves the parallel addition process. Since the number of bits in various digital circuits is being increased, as such, we need millions of transistors to perform several functions in parallel. But it increases the need for surface area, power consumption, noise, and other factors. Therefore, we need to reduce the transistor size to alleviate these problems. In this research article, we designed a 4-bit carry look ahead full adder circuit at several technology nodes using Proteus and then simulated it in Microwind. The designed circuit and layout are presented here. Besides, various operational factors are obtained to observe the benefits of the transistors' size decrement. The layouts are converted and simulated at130 nm.....

Key Words: CMOS; Carry Look Ahead (CLA)Full Adder; Technology Node; VLSI; Area; Power Consumption; Noise; Delay..

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ABSTRACT: Physical design is process of transforming RTL netlist into a layout which is manufacture-able [GDS or GDSII]. An efficient physical design flow is typically divided into five major steps: floorplanning, placement, clock tree synthesis, routing and timing closure. Power optimization is always one of the most important design objectives in modern nanometer IC design. System clock signal in electronics product consumes the important part of dynamic power, among them 70% is spent by clock buffers. This critical problem can be optimized using a technique namely clock gating. Recent studies have shown that applying MBFF is an effective means in reducing clock network power. This paper uses MBFF technique to optimize dynamic power and later clock gating on the same design to achieve better results. The aim of this project is to converge the Server SoC Partition and implement low power techniques such as MBFF and clock gating, to reduce power without degrading timing to a great extent..

Keywords: MBFF; clock gating, dynamic power; power reduction; low power;

[1]. Lekbir Cherif, Mohamed Chentouf, Jalal Benallal, Mohammed Darmi, Rachid Elgouri, Nabil Hmina "Usage and impact of multi-bit flip-flops low power methodology on physical implementation", 4th International Conference on Optimization and Applications (ICOA), DOI: 10.1109/ICOA.2018.8370498, 26-27 April 2018
[2]. Madhushree and Niju Rajan, "Dynamic Power Optimization Using Look- Ahead Clock Gating Technique", 2nd IEEE International Conference On Recent Trends in Electronics Information & Communication Technology (RTEICT), May 19-20, 2017, India.
[3]. Mark Po-Hung Lin, Chih-Cheng Hsu, and Yu-Chuan Chen, "Clock-Tree Aware Multibit Flip-Flop Generation During Placement for Power Optimization", IEEE Transactions On Computer-Aided Design Of Integrated Circuits And Systems, Vol. 34, No. 2, February 2015
[4]. Jitesh Shinde, S. S. Salankar, "Clock gating — A power optimizing technique for VLSI circuits", Annual IEEE India Conference.