iosr-JVSP   Volume-10 ~ Issue-1 ~ Jan. - feb. 2020

ABSTRACT: Co-ordinate rotation Digital computer is the full form of CORDIC is the uncomplicated and structured algorithm to enumerate the problem defined functions such as real and complex multiplications, division, square root etc using simple addition, subtraction and operations like level shifters, hyperbolic and logarithmic functions, calculation of trigonometric. Rectangular to polar and polar to rectangular is an important operations in CORDIC which are generally used in ALUs, wireless communications, DSP processors etc. This type of conversion needs a hardware application of square root and arctangent circuits. The outcome of these applications gives complexity in hardware design, area and power consumption. The CORDIC algorithm is used to overcome these parameters. This paper proposes the experimental results based on various methodologies on design.

Keywords: CORDIC, FPGA, Standard cells, VLSI

[1]. Realization of Cordic Algorithm in DDS: Novel Approach towards Digital Modulators in MATLAB and VHDL, Miss. Prajakta J. Katkar, Dr.Yogesh S. Angal, Department of Electronics and Telecommunication JSPM's BSIOTR COE, Wagholi. Pune, India, 2015 International Conference on Information Processing (ICIP) Vishwakarma Institute of Technology. Dec 16-19, 2015.
[2]. VLSI Architecture Design and Implementation for Application Specific CORDIC Processor, Amritakar Mandal, K. C Tyagi, Brajesh Kumar Kaushik, 2010 International Conference on Advances in Recent Technologies in Communication and Computing.
[3]. VLSI implementation of synchronizer and pipelined CORDIC in OFDM receiver for fourth generation wireless LAN applications, Sudhakara Reddy Penubolu, Ramachandra Reddy Gudheti, 2011 IEEE 3rd International Conference on Communication Software and Networks.
[4]. FPGA Implementation and Power Efficient CORDIC based ADPLL for Signal Processing and Application, Akarshika Singhal, Anjana Goen, TanutrushnaMohapatra, Dept. of Electronics and Communication Engineering, Rustamji Institute of Technology, Gwalior, M.P., India, 2017 7th International Conference on Communication Systems and Network Technologies.
[5]. Real-time FPGA implementation of Hough Transform using gradient and CORDIC algorithm, Si Mahmoud Karabernou and Fayçal Terranti, Image and Vision Computing, Volume 23, Issue 11, 1 October 2005

ABSTRACT: Half-unit-biased (HUB) is a new design that is based on the displacement of the digits represented by half the unit last performed. This arrangement makes the two's complement and round operations closest by avoiding any carry propagation. This saves energy, time and area consumption. Given that the IEEE floating point standard uses unbiased rounding as the default mode, this feature is also desirable for HUB approaches. In this article, we study unbiased rounding for HUB floating point addition both within independent operation and within FMA. We show two different options to eliminate bias by eliminating the sum results either partially or completely. Implementation results of the proposed architecture to help designers decide what their best option.

Keywords: HUB format, unbiased rounding, Floating point , IEEE.

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