iosr-JVSP   Volume-9 ~ Issue-2 ~ March-April 2019

ABSTRACT: The binary addition is the basic arithmetic operation in digital circuits and it became essential in most of the digital systems including ALU, microprocessors and DSP. Adders are the basic building blocks in digital integrated circuit based designs. Ripple Carry Adder (RCA) gives the most compact design but takes longer computation time. The time critical applications use Carry Look-ahead scheme (CLA) to derive fast results but they lead to increase in area. Carry Select Adder is a compromise between RCA and CLA in term of area and delay. This paper focuses on the FPGA implementation of carry select adder design using Spartan xc3s50pq208-4 based on Multiplexer using Verilog. The delay and power is minimized. The proposed architecture of carry select adder is synthesized in Xilinx ISE14.7and implemented in Xilinx ISE 10.1 on Spartan xc3s50pq208-4.

Keywords: Carry select adder, Multiplexer, Full adder, Verilog, FPGA, Spartan, Power, delay, Xilinx ISE14.7, Xilinx ISE10.1.

[1]. Somashekhar Malipatil, R. Basavaraju and Praveen kumar Nartam. "Low Power & High Speed Carry Select Adder Design Using Verilog", IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 6, Issue 6, Ver. II (Nov. - Dec. 2016), PP 77-81 e-ISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197.

[2]. Bejagam Divya, Alekhya Bonkuri, Madhavi Bandi, Somashekhar Malipatil, "Design and verification of low power and high speed carry select adder using Verilog", International Journal of Creative Research Thoughts (IJCRT), ISSN:2320-2882, Volume.6, Issue 1, Page No pp.1786 - 1790, March 2018.

[3]. B. Ramkumarnd Harish M Kittur, "Low Power and Area Efficient Carry Select Adder" IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOL. 20, NO. 2, February 2012.

[4]. B. Ramkumar, Kittur, H.M. and Kannan, P. M. (2010) "ASIC Implementation of Modified Faster Carry Save Adder", Eur. J. Sci. Res., Vol.42, No.1, pp.53–58.

[5]. C.S.Manikandababu "An Efficient CSLA Architecture for VLSI Hardware Implementation" IJMIE, ISSN: 2249-0558, Volume 2, Issue 5, 2012, pp.610-622.

ABSTRACT: Miniaturization being the need of the hour, each system needs to have the least possible area utilized. However in the process of doing the same the speed of the system needs to be considered. As for any system addition is the most basic operation, this paper deals with the analyzing and reviewing of different addition algorithms namely, ripple carry, carry select, carry skip, carry save and carry look ahead adders by performing parallel addition of 8 unsigned numbers each of 12 bits using pipelining technique. Either of the adders above can be used depending on the applications as each of them has tradeoffs in terms of area or speed or power.

Keywords: VLSI, Signal Processing, Adders

[1]. R.P.P. Singh, Parveen Kumar, Balwinder Singh, "Performance Analysis of fast Adders using VHDL", 2009 International Conference on Advances in Recent Technologies in Communication and Computing, October 2009,ISBN: 978-0-7695-3845-7,pp. 189 – 193.
[2]. Mariano Aguirre, Monico Linares, "An Alternative Logic Approach to Implement High-Speed Low-Power Full Adder Cells", SBCCI '05, Proceedings of the 18th annual symposium on Integrated circuits and system design,September 4-7 2005, ISBN: 1-59593-174-0, pp. 166 – 171.
[3]. LuJunming, Shu Yan, Lin Zhenghui and Wang, Ling, "A Novel 10-Transisitor Low-Power High-speed Full Adder Cell", 6th International Conference on Solid-State and Integrated Circuit Technology, October 22-25 2001, ISBN: 0-7803-6520-8, Volume 2, pp. 1155 - 1158.
[4]. Ayman A. Fayed and Magdy A. Bayoumi, "A Low Power 10-Transistor Full Adder Cell for Embedded Architectures",The 2001 IEEE International Symposium on Circuits and Systems, May 6-9 2001, ISBN: 0-7803-6685-9, Volume 4, pp.226 – 229.
[5]. Fatemeh Karami H,Ali K. Horestani, "New Structure for Adder with Improved Speed, Area and Power", International Conference on Networked Embedded Systems for Enterprise Applications, December 8-9 2011, ISBN: 978-1-4673-0495-5, pp. 1-6.

ABSTRACT: An array of numbers or symbols whose values are not based on its preceding value is called Random numbers. The number is said to be random if it does not depends on any calculative algorithm or any seed value. This research paper presents a hardware implementation ofa random number generator using VHDL.The Proposed RNG will be a system where strings of unpredictable bits will be present.Field Programmable Gate Arrays (FPGAs) are an increasingly popular choice of platform for the implementation of cryptographic systems. The random numbers generated by our design are verified against the NIST test for statistical correctness.

Keywords: RNG (random number generator), NIST (National institute of standard and technology).

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