iosr-JVSP   Volume-9 ~ Issue-1 ~ Jan-Feb 2019

ABSTRACT: The work consist of two phases. The first phase of the work aims at finding out the optimized value of the fraction used in fractional filtering for image enhancement techniques in digital image processing. The work is done on MATLAB platform. The work starts with a comparative study of fractional order filter and integer order kernel filters like Sobel and Prewitt filters, used for edge detection and boundary detection of various digital images. With the view of applying fractional filtering in medical images, the work is done by utilizing Magnetic Resonance Imaging (MRI). The noise performances of these filters are analyzed upon the addition of random Gaussian noise. The mean......

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ABSTRACT: The Viterbi algorithm is generally used in decoding convolutional codes utilized in communications. In this paper Viterbi decoder and convolution encoder is designed, used in speech to text conversion.We can utilize three variations for re-computing with operands and itsalterations. The modified full adder circuit is subjected to low power consumption and low area. This can be implemented in Application Specific Integrated circuit (ASIC). This paper explains reduction of power and area by utilization ofmodified full adder. In this,viterbi decoder is designed by utilizing the modified full adder. viterbi decoder and convolution encoder are implemented in speech to text conversion application.

Keywords: Looking forward the procedure, re-computing throughencrypted operands, trellis.

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ABSTRACT: More than 50% of random logic power in an SOC chip is typically consumed by Flip Flop. This is because of redundant transition of internal nodes, when the input and output appear to be in the same state. Different low power techniques have been proposed, but all of these designs use more transistor,leading to an increase in size, which is too costly since flip flops typically account for 50% of random logic area. In this paper we design D flip-flop using 2x1 multiplexer which has reduced transistor count compared to other low power designs of D flip-flops. The focus is to design high speed, low power consumption, positive edge triggered conventional D flip-flop which can be..........

Keywords: D flip-flop, 12 Bit register, Cadence Tool, CMOS circuit, 2x1 Multiplexer

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