iosr-JVSP   Volume-6 ~ Issue-6 ~ Nov-Dec 2016

ABSTRACT: The electroencephalographic signal is a resultant signal of the action potential of neuron in the brain which inspects the neural functions. The brain signal is so subtle that it cannot be analyzed without amplification and this amplified signal is electroencephalogram (EEG). Electroencephalography is non-invasive appliance which is used in observing brain activities and detection of different disorder relating to the human brain. There are several objections of EEG for instance small signal amplitude, synchronizations, artifacts, temporal variability of signal and its sensitivity to noise.

Keywords: Electroencephalogram, EEG,Brain signal, Time domain, Frequency domain

[1]. Zhang xizheng, Yin ling and Wang weixiong, Wavelet Time-frequency Analysis of Electro-encephalogram (EEG) Processing,International Journal of Advanced Computer Science and Application,Vol.1, No. 5, pp. 1-6, 2012.
[2]. M. Teplan, Fundamentals of EEG Measurement, Measurement Science Review, vol. 2, pp. 1–11, 2002.
[3]. Rangaraj M. Rangayyan,Biomedical signal analysis, a case-study approach (John Wiley& Sons, INC 2002).
[4]. Silvia C. and David B. EEG classification using generative independent component analysis(Neurocomputing, 69, pp.769-777, 2006).
[5]. Jalili, M.; Barzegaran, E.; Knyazeva, M.G., Synchronization of EEG: Bivariate and Multivariate Measures, Neural Systems and Rehabilitation Engineering, IEEE Transactions on , vol.22, no.2, pp.212-221, 2014.

ABSTRACT: This paper briefly presents architecture of pre-encoded multipliers for Digital Signal Processing applications based on off-line encoding of coefficients. Complex arithmetic operations are widely used in Digital Signal Processing (DSP) applications. To this extend, the Non-Redundant radix-4 Signed-Digit (NR4SD) encoding technique, which uses the digit values (-1;0;+1;+2) or (-2;-1; 0;+1) is proposed leading to a multiplier design with less complex partial products implementation. To implement some proposed pre-encoded NR4SD multipliers, including the coefficients memory to prove that they are more area and power efficient than the conventional Modified Booth scheme. By this proposed design the performance increases upto25% by decreasing 30%area and power consumption. By this critical path delay also decreases with decrease in area and power consumption

Keywords: Multiplying circuits, Modified Booth encoding, Pre-Encoded multipliers, VLSI implementation

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[5]. O. Kwon, K. Nowka, and E. E. Swartzlander, "A 16-bit by 16-bit MAC design using fast 5: 3 compressor cells," J. VLSI Signal Process. Syst., vol. 31, no. 2, pp. 77–89, Jun. 2002.

ABSTRACT: This paper presents the reduction of logic operations involved in conventional carry select adder (CSLA) and binary to excess -1 converter BEC-based CSLA are analyzed to study the data dependence and to identify redundant logic operations. Here eliminated all the redundant logic operations present in the conventional CSLA, BEC- CSLA and proposed a new logic formulation for CSLA. In the proposed scheme, depending on the initial carry the total operation decides the operation of two individual blocks which itself generates the two final sum's and carry individually

Keywords:Adder, CSLA (Carry Select Adder),Arithmetic unit,low-power design,BEC (binary to excess -1).

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[4]. I.-C. Wey, C.-C. Ho, Y.-S. Lin, and C. C. Peng, "An area-efficient carryselect adder design by sharing the common Boolean logic term," in Proc.IMECS, 2012, pp. 1–4.
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