iosr-JVSP   Volume-6 ~ Issue-3 ~ May-June 2016

ABSTRACT: This paper focuses on the development of 80nm channel length of high-k (TiO2) n-channel (NMOS) and p-channel (PMOS) enhancement mode MOSFETs which emerged due to replacement of SiO2 by high-k (TiO2) MOSFETS, as there were many problems while using SiO2 like high leakage current, short channel and electron tunneling effect.

Keywords: Simulation of the fabrication process was carried out by using Tina Pro Software to obtain more accurate process parameters & the results were then compared with NMOS using SiO2 as gate dielectric.

[1]. Chih Chin Yang, Lan Hui Huang, Bo Shum Chen, Jia Liang Ke, and Chung Lun Tsai National Kaohsiung Marine University, Department of Microelectronics Engineering, Kaohsiung, Taiwan, World Academy of Science, Engineering and Technology, "Inductance Characteristic of Annealed Titanium Dioxide on Silicon Substrate", World Academy of Science, Engineering and Technology, vol. 56, pp. 1-2, 2009.
[2]. Davinder Rathee, Sandeep K Arya, Department of Electronics and Communication Engineering, Guru Jambheshwar University of Science & Technology, Hisar, India, Mukesh Kumar, Department of Electronics Science, Kurukshetra University, Kurukshetra, India, "CMOS Development and Optimization, Scaling Issue and Replacement with High-k Material for Future Microelectronics", International Journal of Computer Applications, vol. 8, no. 5, pp. 10-11, October 2011.

ABSTRACT:The Evolution of Silicon Technology in the Semiconductor Industry is Prevalent . However, as the technology is scaled down to nanometer regime, there is susequent degradation in MOSFET Characteristics. In this Paper, Comparative Analysis of Proposed DG MOSFET device with previous Model was done using Highk Dielectric material and conventional Bulk SiO2 to investigate the various performance characteristics like hreshold Voltage, DIBL, Sub-threshold Voltage and Leakage (OFF) current using COGENDA VTCAD Simulator.......

Keywords: Dielectric, High-k, MOSFET, Scaling, SCEs, Leakage, DIBL, SS

[1]. T.Sood, R.Mehra, "Design A Low Power Half Subtractor Using 90 μm CMOS Technology" ,IOSR Journal of VLSI and Signal Processing, Vol2, issue.3, pp.51-56,2013.
[2]. International Technolgy Roadmap for Semiconductors(http://Public.itrs.net/).
[3]. Y.K. Choi, K. Asano, N.Lindert, V. Subramanian, T.J King, J.Bokor, and C.Hu, "Ultrathin-body SOI MOSFET for Deep-Sub-
[4]. Length Micron Era,"IEEE Electron Device letters, Vol 21, No.5, pp.254, 2000.
[5]. K.Uchida, H.Watanabe, a. Kinoshita,J.Koga, T.Numata, and S.I.Takagi, "Experimental study on carrier transport mechanism in

ABSTRACT:This paper is based on pre layout schematic simulations of a proposed design of 2:1 MDCVSL multiplexer circuit that shows improved performance than the existing 2:1 multiplexer circuit. The proposed design shows superiority in terms of power consumption and temperature sustainability when compared with existing 2:1 CMOS multiplexer and comparative analysis on 90nm technology.....

Keywords: Multiplexer, Adiabatic Logic, Low Power, GDI Logic, MDCVSL Logic.

[1]. Meenakshi Mishra, Shyam Akashe "High performance, low power 200 Gb/s 4:1 MUX with TGL in 45 nm technology" Springer, Applied Nanoscience, Vol 4, Issue 3, pp 271-277 Mar 2014
[2]. Ila Gupta, Neha Arora, B.P. Singh, "An Efficient Design of 2:1 Multiplexer and its Application in 1-Bit Full Adder Cell", International Journal of Computer Applications, Volume 40– No.2, pp 31-36, February 2012
[3]. Debika Chaudhuri, Atanu Nag, Sukanta Bose, Suchismita Mitra, Hemanta Ghosh , "Power and Delay Analysis of a 4 to 1 Multiplexer Implemented in different Logic Style" International Journal of Innovative Research in Science, Engineering and Technology, Volume 4, Special Issue 9, pp 118-123, July 2015
[4]. Yashika Thakur, Rajesh Mehra, Anjali Sharma, " CMOS Design of Area and Power Efficient Multiplexer using Tree Topology", International Journal of Computer Applications, Volume 112, No 11, pp 32-36, February 2015.

ABSTRACT: The paper presents a new design for full adder by utilizing the cascade voltage switch logic. Adders are the basic building block for all the functional units of microprocessors and digital signal processors. In the growing era of nanotechnology, it has become necessary to develop methodologies to efficiently reduce the area and power consumption.......

Keywords: Circuit Simulation, CMOSFET Circuits, CVSL, Full Adder.

[1]. Ranjeeta Verma, Rajesh Mehra, "CMOS Based Design Simulation Of Adder /Subtractor Using Different Foundries", International Journal of Science and Engineering, Vol. 2, Issue 1, pp. 22-27, 2013.
[2]. R. Singh, R. Mehra, "Low power TG full adder design using CMOS nano technology", 2nd IEEE International Conference on Parallel Distributed and Grid Computing, Vol. 2, pp. 210-213, Dec 2012.
[3]. A. Sharma, R. Mehra, "Area and Power efficient CMOS Adder design by hybridising PTL and GDI technique", International Journal of Computer Applications, Vol. 6, Issue 5, pp. 15-22.
[4]. Pradeep Kumar, "Existing Full Adders and Their Comparison on The Basis of Simulation Result And to design a improved LPFA (Low Power Full Adder)" , International Journal of Engineering Research and Applications, Vol. 2, Issue 6, pp. 599-606, Nov-Dec 2012.