iosr-JVSP   Volume-5 ~ Issue-6 ~ Nov-Dec 2015

ABSTRACT: Addition is most commonly performed arithmetic operation.Adder is basic building block of most of digital systems. Improvement in speed of adder indirectly improves speed of system. Hence careful design optimization is required. VHDL coding of different adders is done and comparative analysis is made. Each adder has its own positives and negatives in terms of speed and area. Various adders are designed using VHDL. Then, they are simulated and synthesized using Xilinx ISE 9.2i for Spartan 3E family device with speed grade -5.

Keywords – Adder, Carry Look Ahead, Carry Save Adder, Ripple Carry Adder, FPGA

[1] R.UMA, Vidya Vijayan , M. Mohanapriya, Sharon Paul," Area, Delay and Power Comparison of Adder Topologies", International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, February 2012.
[2] Animul islam, M.W. Akram, S.D. pable ,Mohd. Hasan, "Design and Analysis of Robust Dual Threshold CMOS Full Adder Circuit in 32 nm Technology", International Conference on Advances in Recent Technologies in Communication and Computing,2010.
[3] Deepa Sinha, Tripti Sharma, k.G.Sharma, Prof.B.P.Singh, "Design and Analysis of low Power 1-bit Full Adder Cell",IEEE, 2011.
[4] V.Krishna Kumari, Y.Sri Chakrapani," Designing and Characterization of koggestone, Sparse Kogge stone, Spanning tree and Brentkung Adders" International Journal of Modern Engineering Research (IJMER) Vol. 3, Issue. 4, July-august. 2013 pp-2266-2270

ABSTRACT: The hike in internet usage globally and the ascending number of its users have ensued to high demands for high speed data communication systems enriched with faster processors and high speed interfaces to peripheral components. With the advent to QDR SRAMs these requirements of this evolving system are fulfilled. The QDR SRAM enables the system to work on four times the bandwidth when compared to other SRAM architectures. For proper functioning of these SRAMs we introduce a design of QDR II+ controller which serves the purpose of translating memory requests issued by the hardware to which the RAM has been interfaced, into data and control signals for the SRAM while complying to the timing requirements imposed by the memory configurations.

Keywords: FPGA, QDR II+ memory, IP core, SoC, Verilog

[1]. Altera Corporation, AN 461: Design Guidelines for Implementing QDRII+ and QDRII SRAM Interfaces in Stratix III and Stratix IV Devices. February 2010.
[2]. Altera Corporation, AN 326: Interfacing QDRII+ & QDRII with Stratix II, Stratix II GX, Stratix, & Stratix GX Devices.
[3]. Cypress Semiconductor Corporation.CY7C1302V25 9-Mb Pipelined SRAM with QDR™ Architecture. May 2008.
[4]. Steven M. Rubin, Computer Aids for VLSI Design, Addison-Wesley, 1987.
[5]. Jack Truong. (March 31st, 2005). Evolution of Network Memory. [Online]. Available: http://www.jedex.org/
[6]. Markus Ringhofer, "Design and Implementation of a Memory Controller for Real-Time Applications," Institut fur Technische Informatik ¨ Technische Universit¨at Graz

ABSTRACT: Text to speech synthesis (TTS) is the production of artificial speech by a machine for the given text as input. The speech synthesis can be achieved by concatenation and Hidden Markov Model techniques. The voice synthesized by these techniques should be evaluated for quality. The study extends towards the comparative analysis for quality of speech synthesis using hidden markov model and unit selection approach. The quality of synthesized speech is analyzed for subjective measurement using mean opinion score and objective measurement based on mean square score and peak signal-to-noise ratio (PSNR). The quality is also accessed by Mel-frequency cepstral coefficient features for synthesized speech. The experimental analysis shows that unit selection method results in better synthesized voice than hidden markov model.

Keywords: TTS, MOS, HMM, Unit Selection, Mean, Variance, MSE, PSNR.

[1]. Mohammed Waseem, C.N Sujatha, ―Speech Synthesis System for Indian Accent using Festvox‖, International journal of Scientific Engineering and Technology Research, ISSN 2319-8885 Vol.03,Issue.34 November-2014, Pages:6903-6911
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[3]. S. Martincic- Ipsic and I. Ipsic, ―Croatian HMM Based Speech Synthesis,‖ 28th Int. Conf. Information Technology Interfaces ITI 2006, pp.19-22, 2006, Cavtat, Croatia.
[4]. Alex Acero, ―Formant Analysis and Synthesis using Hidden Markov Models‖. Proceedings of Eurospeech conference. September 1999
[5]. R.sproat, J. Hirschberg, and D. Yarowsky, ―A corpus-based synthesizer‖, Proc. ICSLP, pp.563-566, 1992.
[6]. T.Yoshimura, K.Tokuda, T. Masuko, T. Kobayashi and T. Kitamura,―Simultaneous Modeling of Spectrum, Pitch and Duration in HMM-Based Speech Synthesis‖In Proc. of ICASSP 2000, vol 3, pp.1315-1318, June 2000.