Version-1 (July-August 2015)
- Citation
- Abstract
- Reference
- Full PDF
| Paper Type | : | Research Paper |
| Title | : | Implementation of ASIC For High Resolution Image Compression In Jpeg Format |
| Country | : | India |
| Authors | : | M.Asha || B.Chinna Rao |
ABSTRACT: Increase in multimedia applications drastically increased the demand for digital information. Reduction in the size of this data for transmission and storage is very important. This is done by Image compression. JPEG (Joint Photographic Experts Group) is an international compression standard for continuous-tone still image, both grayscale and color. There are software solutions as well as hardware solutions for JPEG compression depending upon the application. Hardware solutions are mainly used for high speed and parallel processing applications. As the distinct requirement for each of the applications, the JPEG standard has two basic compression methods.
[1]. Digital Integrated Circuits A Design Perspective 2nd Ed- Rabey
[2]. A Low Area Pipelined 2-D DCT Architecture for JPEG Encoder by Qihui Zhang, Nan Meng
[3]. D. Trang, N. Bihn, "A High-Accuracy and High-Speed 2-D 8x8 Discrete Cosine Transform Design". Proceedings of ICGC-RCICT 2010, vol. 1, 2010, pp. 135-138
[4]. Pipelined Fast 2-D DCT Architecture for JPEG Image Compression by Lucian0 Volcan Agostini, Ivan Saraiva Silva, Sergio Bampi
[5]. Parallel-Pipeline 8 8 Forward 2-D ICT Processor Chip for Image CodingGustavo A. Ruiz, Juan A. Michell, and Angel M. Burón
- Citation
- Abstract
- Reference
- Full PDF
| Paper Type | : | Research Paper |
| Title | : | Implementation of 2-D Dct Architecture for Optimized Area And Power Utilization |
| Country | : | India |
| Authors | : | G, Ravi kumar || G. Sateesh Kumar |
ABSTRACT:In this paper, a new approach for 2-D DCT architecture is introduced where both area and power are improved simultaneously. To reduce the area the proposed architecture is designed with tristate buffers. It can calculate first-dimensional and second-dimensional transformations simultaneously by using 1-D discrete cosine transform (DCT) core to reach less hardware utilization. Modules in the 1-D DCT core, including the modified two-input butterfly (MBF2), the pre-reorder, the process element even (PEE), the process element odd (PEO), and the post reorder are designed using the VERILOG HDL.
[1]. A. M. Shams, A. Chidanandan , W. Pan, and M. A. Bayoumi, "NEDA: A low-power high performance DCT architecture," IEEE Trans. Signal Process., vol. 54, no. 3, pp. 955–964, Mar. 2006.
[2]. A. Madisetti and A. N. Willson , "A 100 MHz 2-D 8 X 8 DCT/IDCT processor for HDTV applications," IEEE Trans. Circuits Syst. Video Technol., vol. 5, no. 2, pp. 158–165, Apr. 1995.
[3]. A. Tumeo, M. Monchiero, G. Palermo, F. Ferrandi, and D. Sciuto, "A pipelined fast 2DDCTaccelerator for FPGA-based SOCs," in Proc. IEEE Comput. Soc. Annu. Symp. VLSI., 2007, pp. 331– 336.
[4]. C. C. Sun, P. Donner, and J. Gotze, "Low complexity multi-purpose IP core for quantized discrete cosine and integer transform," in Proc. IEEE Int. Symp. Circuits Syst.,2009, pp. 3014–3017.
[5]. C. Peng , X. Cao, D. Yu, and X. Zhang, "A 250 MHz optimized distributed architecture of 2D 8 x 8 DCT," in Proc. Int. Conf. ASIC, 2007, pp. 189–192.
- Citation
- Abstract
- Reference
- Full PDF
| Paper Type | : | Research Paper |
| Title | : | Performance Evaluation of Image Processing Algorithms for Underwater Image Enhancement in FPGA |
| Country | : | India |
| Authors | : | Alex Raj S. M. || Khadeeja N. || Supriya M. H. |
ABSTRACT: Underwater photography is challenging due to poor illumination and varying environment condition. Due to the insufficient illumination provided by the Automated Underwater Vehicles (AUV), the obtained degraded images need to be enhanced. Image enhancement techniques have to be implemented in hardware to be used with AUVs. Field Programmable Gate Arrays (FPGA) have been proved to be a better option for being used in image processing techniques due to it's inherit parallelism.
[1]. Retrieved from : http://www.bbc.co.uk/history/ancient/archaeology/marine_01.shtml
[2]. Erhardt – Ferron ;Theory and Applications of Digital Image Processing university Of Applied sciences of fenburg hochschule for technik undwirt schaft
[3]. Beilei Xu; Yiqi Zhuang; Hualian Tang; Li Zhang, "Object-based multilevel contrast stretching method for image enhancement," Consumer Electronics, IEEE Transactions on , vol.56, no.3, pp.1746,1754, Aug. 2010.
[4]. Kim, Tae Keun, Joon Ki Paik. and Bong Soon Kang. Contrast enhancement system using spatially adaptive histogram equalization with temporal filtering. Consurner Electronics, IEEE Transactions on 44, no. I (1998): 82-87
[5]. Jiang Duan; Wenpeng Dong; Rui Mu; Guoping Qiu; Min Chen, "Local contrast stretch based tone mapping for high dynamic range images," Computational Intelligence for Multimedia, Signal and Vision Processing (CIMSIVP), 2011 IEEE Symposium on , vol., no., pp.26,32, 11-15 April 2011
[6]. Eramian, M.; Mould, D., "Histogram equalization using neighborhood metrics," Computer and Robot Vision, 2005. Proceedings. The 2nd Canadian Conference on , vol., no., pp.397,404, 9-11 May 2005