iosr-JVSP   Volume-5 ~ Issue-2 ~ Mar-Apr 2015

ABSTRACT: Generally, Speech enhancement aims to improve speech quality and intelligibility of a noise contaminated speech signal by using various signal processing approaches. Removal of a noise from a noisy speech is a common problem; already a vast research was carried out in earlier. However, due to the characteristics of various types of noises, the approaches proposed in earlier are not applicable for all types of noises. In addition, the earlier approaches didn't focus on the non-linear and non-stationary characteristics on noise environments. EMD is a filtering approach performs efficiently for non-stationary environments. This paper proposes a novel EMDF approach with the inspiration of thresholding to remove the noise from noisy speech sample. The proposed approach also developed a method to select the IMF index for separating the residual low-frequency noise components from the speech estimate, based on the IMF statistics. An experimental study was also done on various types of noise contaminated speech samples like babble noise, restaurant noise and car interior noise at various strengths.

Keywords: Speech enhancement, EMDF, IMF, noise estimation, SegSNR.

[1]. I. Cohen and B. Berdugo, "Speech enhancement for non-stationarynoise environments", in Signal Processing. Amsterdam, the Netherlands:Elsevier, Nov. 2001, vol. 81, pp. 2403–2418.
[2]. Sohn J. and Kim N, "Statistical Model based voice activity detection", IEEE Signal Processing Letters, Jan 1999, Volume:6 , Issue: 1 ) pp.1-3.
[3]. Shrinivasan K. and Gersho A. (1993), "Voice ActivityDetection for Cellular Network", Prec. IEEE Speech CodingWorkshop pp. 85-86.
[4]. R. Martin, "Noise PSD estimation based on optimal smoothing andminimum statistics," IEEE Trans. Speech Audio Process., vol. 9, no. 5,pp. 504–512, Jul. 2001.
[5]. I. Cohen, "Noise spectrum estimation in adverse environments: Improvedminima controlled recursive averaging," IEEE Trans. SpeechAudio Process., vol. 11, no. 5, pp. 466–475, Sep. 2003.
[6]. Tien Dung Tran, "Speech enhancement using modified IMCRA and OMLSA methods", Third International Conference on Communications and Electronics (ICCE), Aug. 2010.
[7]. Anuradha R. Fukane, Shashikant L. Sahare, "Noise estimation Algorithms for Speech Enhancement in highlynon-stationary Environments", IJCSI International Journal of Computer Science Issues, Vol. 8, Issue 2, March 2011ISSN (Online): 1694-0814.

ABSTRACT: This paper is devoted for the design of an optimized high speed Vedic multiplier using Udhava-Tiryakbhyam sutra. High speed multiplier is required to perform critical multiplication operation of Digital Signal processing applications like DFT,FFT, convolution , Arithmetic and logic unit(ALU) and Multiply and Accumulate(MAC). This paper shows the Multiplier architecture for 2×2, 4×4,8×8 and 16×16 .The performance has been evaluated in XILINX ISE 9.2.Synthesis and simulation have been performed for various architectures considering delay, number of slices, power and area.

Keywords: Vedic Mathematics, Vedic multiplier, Udhava- Tiryakbhyam, Array multiplier, Booth Algorithm, Digital Signal Processing, VLSI Signal processing, Verilog.

[1]. Rutuparna panda,M.pradhan," Speed comparision of 16*16 vedic multipliers" IJCA,vol-21,may-2011
[2]. M.Pradhan, R.Panda, S K Sahu, " MAC Implementation using Vedic Multiplication Algorithm," IJCA (0975-8887), Vol-21, No.7, may 2011.
[3]. M.Pradhan, R.Panda, "Design and Implementation of Vedic Multiplier," A.M.S.E. Journal, vol.15, Issue 2,pp.1-19, July 2010.
[4]. A Nanda, S Behera, "Design and Implementation of Urdhva-Tiryakbhyam Based 8×8 Vedic Binary Multiplier", IJERT, Vol.3,Issue 3, March 2014.
[5]. Poornima M, Shivaraj Kumar Patil, Shivukumar , Shridhar K P , Sanjay H, "Implementation of Multiplier using Vedic Algorithm", International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-2, Issue-6, May 2013.
[6]. Premananda B.S., Samarth S. Pai, Shashank B., Shashank S. Bhat "Design and Implementation of 8-Bit Vedic Multiplier " International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (An ISO 3297: 2007 Certified Organization) Vol. 2, Issue 12, December 2013.

ABSTRACT: SRAM is a memory component and is used in various VLSI chips due to its unique capability to retain data. This memory cell has become a subject of research to meet the demands for future communication systems. In this paper a 6T SRAM cell is designed by using cadence virtuoso EDA tool in 180nm CMOS technology. Its performance characteristics such as power dissipation, delay, and power delay product are analysed. Power dissipation, delay, and power delay product of the designed 6T SRAM cell are 54.63 x10-9 W, 19.96 x10-9s, and 1070.45 x 10-18 Ws respectively.

Keywords: Power, Delay, Power delay product, 6T SRAM cell.

[1] P. Athe, and S. Dasgupta, A Comparative Study of 6T, 8T and 9T Decanano SRAM cell, IEEE Symposium on Industrial Electronics and Applications, 2, 2009, 889-894.
[2] R. K. Sah, I. Hussain, and M. Kumar, Performance Comparison for Different Configurations of SRAM Cells, International Journal of Innovative Research in Science, Engineering and Technology, 4, 2015, 18543-18546.
[3] N. Rahman, and B. P. Singh, Design of Low Power SRAM Memory Using 8T SRAM Cell, International Journal of Recent Technology and Engineering, 2, 2013, 123-127.
[4] A. Agal, Pardeep, and B. Krishan, 6T SRAM Cell: Design and Analysis, Journal of Engineering Research and Applications, 4, 2014, 574-577.
[5] D. Aggarwal, P. Kaushik, and N. Gujran, A Comparative Study of 6T, 8T and 9T SRAM Cell, International Journal of Latest Trends in Engineering and Technology, 1, 2012, 44-52.

ABSTRACT: In this paper performance analysis comparison of a conventional wallace multiplier and a reduced complexity wallace multiplier is presented. Performance comparison is done in terms of power, delay, power delay product and complexity in terms of number of MOS transistors. The multipliers are designed by using Cadence virtuoso in 180nm CMOS technology and their performance characteristics are analysed. Performance improvement of the designed 4x4 bit reduced complexity wallace multiplier with respect to the designed 4x4 bit conventional wallace multiplier in terms of number of transistors, delay and power delay product are found to be 12.05%, 9.42% and 4.98% respectively.

Keywords: Power, Delay, Power delay product, Reduced complexity, Conventional wallace multiplier, Reduced complexity wallace multiplier.

[1] C. S. Wallace, A Suggestion for a Fast Multiplier, IEEE Transactions on Computers, 13, 1964,14-17.
[2] D. R. Gandhi, and N. N. Shah, Comparative Analysis for Hardware Circuit Architecture of Wallace Tree Multiplier, IEEE International Conference on Intelligent Systems and Signal Processing, Gujarat, 2013, 1-6.
[3] C. Vinoth, V. S. K. Bhaaskaran, B. Brindha, S. Sakthikumaran, V. Kavinilavu, B. Bhaskar, M. Kanagasabapathy, and B. Sharath, A Novel Low Power and High Speed Wallace Tree Multiplier for RISC Processor, IEEE 3rd International Conference on Electronics Computer Technology, Kanyakumari, 2011, 330-334.
[4] Hussain, and M. Kumar, Design and Analysis of a Conventional Wallace Multiplier in 180nm CMOS Technology, IOSR Journal of VLSI and Signal Processing, 5, 2015, 60-65.
[5] E. E. Swartzlander, and R. S. Waters, A Reduced Complexity Wallace Multiplier Reduction, IEEE Transactions on Computers, 59, 2010, 1134-1137.