iosr-JVSP   Volume-5 ~ Issue-1 ~ Jan-Feb 2015

ABSTRACT: High integration density, low power and fastperformance are all critical parameters in designing of memory blocks. Static Random Access Memories (SRAMs)'s focusing on optimizing dynamic power concept of virtual source transistors is used for removing direct connection between VDD and GND. Also stacking effect can be reduced by switching off the stacktransistors when the memory is ideal and the leakage current using SVL techniques This paper discusses the evolution of 9t SRAM circuits in terms of low power consumption, The whole circuit verification is done on the Tanner tool, Schematic of the SRAM cell is designed on the S-Edit and net list simulation done by using T-spice and waveforms are analyzed through the W-edit.

Keywords: Leakage Current; Low Power; SRAM; Stack tech; SVL; VLSI; USVL; LSVL; VTCMOS; MTCMOS.

[1]. ShyamAkashe, Meenakshi Mishra, and Sanjay Sharma, Self controllable voltage level circuit for low power, high speed 7TSRAM cell at 45nm
[2]. Design Of Efficient Low Power 9t Sram Cell , K.Gavaskar1 S.Priya2 1P.G Scholar/VLSI Design, 2Assistant professor ECE,Bannari Amman Institute of Technology Sathyamangalam, India. Vol. 2 Issue 1, January- 2013-(IJERT)
[3]. Performance Evaluation of Different SRAM Schemes in 16nm Predictive Technology, Swati Vijayvergia Vol. 4 Issue 10, January- 2013-(IJERT)
[4]. A.J. Bhavnagarwala, X. Tang, and J. Meindl,\The simpact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability," IEEE Journal of Solid State Circuits, vol. 36, No. 4, pp. 658-665,April 2001.
[5]. Leakage Reduction and Stability Improvement Techniques of 10t SRAM Cell: A Survey A.VeeraLakshmi, S.Priya, (IJITEE) ISSN: 2278-3075, Volume-3, Issue-7, December 2013.
[6]. Design a 5T SRAM by using self controllable voltage level leakage reduction technique with CMOS Technology Laxmi Singh1, Ajay Somkuwar2 1Department of Electronics & Communication, Corporate college
[7]. of Technology, Bhopal, INDIA. 2Department of Electronics & Communication Bhopal, MP, INDIA .

ABSTRACT:This paper is base on the implementation of Reduce Instruction set computer with the application of Discrete Cosine transform (DCT) , Inverse DCT, Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT), Digital filter are performed by DSP system. Digital filter is one of the important contents of digital signal process. The performance of the processor design is improved by using the pipeline approach. It allows the processor to work on different steps of the instruction at the same time, thus more instruction can be executed in a shorter period of time. The analysis of this processor will provide various features including arithmetic operations. The speed of operation is mainly affected by the computational complexity due to multipliers and adder modules of the digital systems. Our work will targets the computer architecture courses and presents an FPGA (Field Programmable Gate Array) implementation of a MIPS (Microprocessor without Interlocked Pipeline Stages) via VHDL (Very high speed integrated circuit Hardware Description Language) design. The latency and computational time is utmost important in microprocessor. Thus we design the multiplier and adder module with improve latency and computational time.

Keywords: IIR FILTER, FPGA, DSP Processor, VHDL

[1] Sheikh Md. Rabiul Islam, Robin Sarker, Shumit Saha, A. F. M. Nokib Uddin " Design of a programmable digital IIR filter based on FPGA" IEEE International Conference on Infonnatics, Electronics & Vision ICIEV year 2012.
[2] Amit Kumar Singh Tomar, Rita Jain "20-Bit RISC & DSP System Design in an FPGA" IEEE international conference in year 2013.
[3] Chaohua Dai, Weirong Chen, and Yunfang Zhu "Seeker Optimization Algorithm for Digital IIR Filter Design" IEEE Transactions On Industrial Electronics, Vol. 57, No. 5, May 2010 pp no. 1710.
[4] ZHANG Jian-ping, PAN Ling-ling, DING Quan-fei "IIR Digital Filter Design Based on DSP and SOPC" International Symposium on Intelligence Information Processing and Trusted Computing year 2010.

ABSTRACT: Segmentation technique plays a major role in scripting the documents for extraction of various features. Many researchers are doing various research works in this field to make the segmenting process simple as well as efficient. In this paper a simple segmentation technique for both the line and word segmentation of a script document has been proposed. The main objective of this technique is to recognize the spaces that separate two text lines.For the Word segmentation technique also similar procedure is followed. In this work ,three different scanned document have been taken as input images for both line and word segmentation techniques. The results found were outstanding with average accuracy for both line and word. It provides 100% accuracy for line segmentation and 100% for line segmentation as well. Evaluation results show that our method outperforms several competing methods.

Key Words: Segmentation, Line Segmentation, Word Segmentation, Devanagiri Script, Machine learning, shirorekha, white rows, white columns, consecutive white rows (CWR) threshold

[1]. Vikash J Dhongre, Vijay H Mankar, "International Journal Of Computer Science, Engineering and information Technology(IJCSEIT)",Vol 1,No.3,August 2011
[2]. Naresh Kumar Garg, Lakhwinder Kaur, M. K. Jindal, "International journal of computer Applications(0975-8887)",Volume 1-No.- 4,2010
[3]. Nallapareddy Priyanka, Srikanta Pal, Ranju Mandal, (2010) "Line and Word Segmentation Approach for Printed Documents", IJCA Special Issue on Recent Trends in Image Processing and Pattern Recognition-RTIPPR, pp 30-36
[4]. Raghuraj Singh, C. S. Yadav, Prabhat Verma, "Optical Character Recognition (OCR) for Printed Devnagari Script Using Artificial Neural Network", International Journal of Computer Science & Communication, 2010.
[5]. M. K. Jindal, R. K. Sharma and G. S. Lehal, "Structural Features for Recognizing Degraded Printed Gurmukhi Script", in Proceedings of the IEEE 5th International Conference on Information Technology: New Generations (ITNG 2008), pp. 668-673, April 2008.

ABSTRACT: Object tracking is a process devoted to locate the pathway of moving object in the succession of frames. The tracking of the object has been emerged as a challenging facet in the fields of robot navigation, military, traffic monitoring and video surveillance etc. In the first phase of contributions, the tracking of object is exercised by means of matching between the template and exhaustive image through the Normalized Cross Correlation (NCCR). In order to update the template, the moving objects are detected using frame difference technique at regular interval of frames. Subsequently, NCCR or Principal Component Analysis (PCA) or Histogram Regression Line (HRL) of the template and moving objects are estimated to find the best match to update the template. The second phase discusses the tracking of object between the template and partitioned image through the NCCR with reduced computational aspects. However, the updating schemes remain same. Here, an exploration with varied bench mark dataset has been carried out. Further, the comparative analysis of the proposed systems with different updating schemes such as NCCR, PCA and HRL has been succeeded. The offered systems considerably reveal the capability to track an object indisputably under diverse illumination conditions.

Keywords: Centroid, Frame difference, Histogram Regression Line, Normalized Cross Correlation, Template updating, Object Tracking

[1]. A.Yilmaz, O.Javed and M.Shah, Object tracking: A survey, ACM, Computing Surveys, 38, 4, Article 13, Dec. 2006.
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workshop on Visual information processing, Australia, June, 2004, pp.95-98.
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Intell. 22, 8, 2000, pp.809–830.
[4]. L. Wang, W. Hu and T. Tan, Face tracking using motion guided dynamic template matching, Proceedings of the 5th Asian
Conference on Computer Vision -ACCV2002, Melbourne, Australia, January, 2002, pp.1-6
[5]. J.P. Lewis, Fast Normalized Cross-Correlation, Vision Interface, 1995, pp.120-123.