iosr-JVSP   Volume-4 ~ Issue-5 ~ Sep-Oct 2014

ABSTRACT: This paper deals with the reduction of power dissipation in the basic logic circuit like NAND gate and NOR gate by using transistor stacking technique. The logic gates are designed using 130nm technology parameter and are simulated using PSPICE. The input vector combinations are compared with the simulated result on the basis of propagation delay and power consumption. It is found that when the number of low-input increases in case of NAND gate the power dissipation decreases but the delay increases and for NOR gate power dissipation decreases with the increase in high input vector combinations.

Index Terms: Low Power, Propagation Delay, Power Dissipation, Sub-threshold current, stacking effect.

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[5]. Sreenivasa Rao Ijjada, B. Ramparamesh, "Reduction of Power Dissipation in Logic Circuits", International Journal of Computer Applications, Vol. 29-No. 6, June 2011.

ABSTRACT: Multiplication is the commonly used operations in a Central Processing Unit (CPU). The performance of the CPU depends on multiplier which may be slower and may consume significant amount of power. This work presents a low power and high speed multiplier architecture using Vedic mathematics technique. The work also proves the efficiency of Urdhava Tiryakbhyam sutra of Vedic mathematics which shows a difference between actual process of multiplication and Vedic multiplication. Carry Save Adder (CSA) is used in the architecture to have reduced delay. The proposed multiplier circuit is synthesized using Xilinx 13.1 version tool for Field Programmable Gate Array (FPGA) flow and Cadence 12.10 version tool for Application Specific Integrated Circuit (ASIC) flow for the analysis of dynamic power consumption and propagation delay and the design is simulated using Modelsim 6.5 version tool for functional verification.

Keywords: ASIC flow, CSA, FPGA flow, Vedic mathematics, Urdhava Tiryakbhyam sutra

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[4]. Akhalesh K, Itawadiya, Rajesh Mahle, Vivek Patel and Dadan Kumar, Design a DSP operations using vedic mathematics: IEEE International Conference on Communications and Signal Processing (ICCSP), Melmaruvathur, 3-5 April 2013, pp. 897-902.

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ABSTRACT: Versa Module Europa (VME) bus is used in various applications in order to ensure safety and security. VME64x based Real Time Computer (RTC) system with various types of Input / Output (I/O) hardware modules is being designed and developed for use in various safety critical and safety related Instrumentation & Control (I&C) systems. Analog Output Card (AOC) is one of the I/O hardware modules as part of VME64x RTC development. The AOC uses Field-Programmable Gate Array (FPGA) as VME bus system controller. This paper discusses the design and development of a VME64x bus controller so as to meet the required specifications correctly.

Keywords: A16/A24/D16 Bus interface, Analog Output Card (AOC), Field Programmable Gate Array (FPGA), VHSIC Hardware Description Language (VHDL), VME64x bus

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