iosr-JVSP   Volume-4 ~ Issue-2 ~ March-April 2014

ABSTRACT: Image fusion is to integrate complementary multisensor, multitemporal and multiview data into one new image containing data of quality which cannot be achieved otherwise. As optical lenses in capturing device have limited depth-of-focus , it is sometime not possible to obtain an image that contains all relevant objects, in focus. To achieve all objects in focus, a fusion process is required which focuses all objects.The solution to this problem is the new architecture called Hybrid Image Fusion which .involves physical image alignment by using image registration ,then applying DWT. In the intermediate stage the images are decomposed and further fused to obtained hybrid image by using pixel rules.

Keywords: D.W.T , Image Registration, Hybrid Image Fusion , Multiresolution , Pixel rules

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ABSTRACT: Sensor network consists of tiny sensors and actuators with general purpose computing elements to cooperatively monitor physical or environmental conditions such as temperature, pressure, etc. Wireless Sensor Networks are uniquely characterized by properties like limited power they can harvest or store, dynamic network topology, large scale of deployment. To increase the network lifetime we used energy efficient communication protocol known as Low Energy Adaptive Clustering Hierarchy (LEACH). Low Energy Adaptive Clustering Hierarchy (LEACH) is an energy-efficient hierarchical-based routing protocol. Our prime focus was on the analysis of LEACH based upon parameter network lifetime reducing the power consumption of wireless sensor networks.

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ABSTRACT:Two's complement multipliers are important for a wide range of applications. In this paper, we present a technique to reduce by one row the maximum height of the partial product array generated by a radix-4 Modified Booth Encoded multiplier, without any increase in the delay of the partial product generation stage. This reduction may allow for a faster compression of the partial product array and regular layouts. This technique is of particular interest in all multiplier designs, but especially in short bit-width two's complement multipliers for high-performance embedded cores.

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