iosr-JEEE   Volume-8 ~ Issue-4

Abstract: This paper explains the design of a simple RISC processor and procedure for simulating it. A Reduced Instruction Set compiler (RISC) is a microprocessor that had been designed to perform a small set of instructions, with the aim of increasing the overall speed of the processor along with reducing the power consuming while executing the instruction. The RISC architecture follows the philosophy that one instruction should be performed every cycle. This work presents the design and implementation of a 32 bit RISC soft core processor intended for computer architecture introduction considered to be an effective solution for computer comprehension. The idea of this project was to create a microprocessor as a building block in VHDL than later easily can be included in a larger design. It will be useful in systems where a problem is easy to solve in software but hard to solve with control logic. A state machine dedicated to the function can of course replace the microprocessor and associated software. However at a high level of complexity it is easier to implement the function in software. In this project Modelsim is used for logical verification and further synthesizing is carried on Xilinx-ISE tool. To perform the power analysis the Xilinx xpower analyzer is used.

Keywords: Low Power, Speed, RISC, Processor, Xilinx.

[1] Pan-Song, Huang-JiYe, SOPC Technology Utility Tutorial, Tsinghua University Press, 2006.
[2] Zheng-WeiMin, Tang-ZhiZhong. Computer System Structure (The second edition), Tsinghua University Press, 2006.
[3] Ramdas, T. Li-Minn Ang and Egan, G., "FPGA implementation of an integer MIPS processor in Handel-C and its application to human face detection," in Proc. of IEEE Region 10 Conference, Vol. 1, pp. 36-39, 2004.
[4] Xizhi Li and Tiecai Li, "ECOMIPS: an economic MIPS CPU design on FPGA," in Proc. of the 4th IEEE International Workshop on System-on- Chip for Real-Time Applications, pp. 291-294, 2004.
[5] D. M. Harris and S. L. Harris, Digital Design and Computer Architecture,1st edition, Morgan Kaufmann, 2007, USA.

Abstract: This paper presents an error detection method with majority logic decoding. The majority logic decodable words are suitable for memory application due to their capability to correct large number of errors, but they require a large decoding time that impacts the memory performance. So in the proposed fault detection method they significantly reduce the memory access time. Keywords: Triple Modular Redundancy, Error Correction Codes, Majority Logic, Low Density parity checks, Difference Set Cyclic Codes, Syndrome Fault Detector, Majority Logic Detector/Decoder.

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Abstract: The binary adder is the critical element in most digital circuit designs including digital signal processors (DSP) and microprocessor data path units. As such, extensive research continues to be focused on improving the power delay performance of the adder. In VLSI implementations, parallel-prefix adders are known to have the best performance. Parallel-prefix adders (also known as carry-tree adders) are known to have the best performance in VLSI designs. This paper investigates three types of carry-tree adders (the Kogge-Stone, sparse Kogge-Stone, and spanning tree adder) and compares them to the simple Ripple Carry Adder (RCA). In this project Xilinx-ISE tool is used for simulation, logical verification, and further synthesizing .

Keywords: DSP, Adders, Delay, Power.

[1] B. Ramkumar and Harish M Kittur , ― Low-Power and Area-Efficient Carry Select Adder ―, IEEE Transactions on very large scale integration (VLSI) systems, vol.20, no.2,pp.371-375, Feb .2012

[2] Dilip P. vasudevan, parag k.lala, james patrik parkerson, ― Self- checking carry-select adder design based on two rail en-coding‖,IEEE Trans, CIRCUITS AND SYSTEMS—I , December 2007

[3] http://en.wikibooks.org/wiki/Digital_Circuits/Adders.html

[4] Yu-Ting Pai and Yu-Kumg Chen, ―The fastest carry look ahead adder,‖ IEEE trans . International Workshop on Electronic Design, Test and Applications,vol.22. Feb .2004

[5] http://umunhum.stanford.edu /farland/notes.html

[6] Dayu Wang, Xiaoping Cui, Xiaojing Wang, ―Optimized design of Parallel Prefix Ling Adder,‖IEEE Trans. pp.941-944, oct.2011 [7] B.Bhaskar, M.Kanagasabapathy, V.S.Kanchana Bhaaskaran, ―A hybrid adiabatic parllel prefix addition scheme for low power‖, IEEE Trans , International Conference on Recent Trends in Information Technology, pp.389-393 , june 2011 [8] G. W. Hanson, Fundamentals of Nanoelectronics. Englewood Cliffs,NJ: Prentice-Hall, 2008.

[9] R. Zhang, K. Walus, W. Wang, and G. A. Jullien, ―Performance comparisonof quantum-dot cellular automata adders,‖ in Proc. IEEE Int. Symp.Circuits Syst., 2005, pp. 2522–2526.

[10] Architecture of FPGAs and CPLDs: A Tutorial - Computer ...www.eecg.toronto.edu/~jayar/pubs/brown/survey.pdfFile Format: PDF/Adobe Acrobat - Quick View.