Abstract: A model for MIS device in accumulation is proposed which includes a bias and frequency dependent conductance in parallel with the insulator capacitance due to the leakage current. The model is validated by experimental results on MOS structures fabricated on n<100>Si having about 9 nm dry thermal oxide. The real and imaginary impedance versus frequency plots of such MOS device having large conductance can be used to determine accurately the oxide capacitance and consequently the oxide thickness without the use of ellipsometer. Greatly reduced MIS dot area can assist in avoiding frequency dispersion in accumulation capacitance, particularly at small-signal frequency of 1 MHz which is commonly used for generating high frequency C-V plots.
Key Words: Metal-Insulator-Semiconductor, Impedance, Conductance
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