iosr-JCE   Volume-13 ~ Issue-4

Paper Type	:	Research Paper
Title	:	Review of FPGA-based design methodologies for efficient hardware Area estimation
Country	:	India
Authors	:	Ms. Rachna Singh, Dr. Arvind Rajawat
	:	10.9790/0661-1340106

Abstract: In recent years, FPGA's have become increasingly important and have found their way into system design. So, the desire emerges for a means that allows early area and performance estimation Understanding how a design maps to them and consumes various FPGA resources can be difficult to predict, so typically designers are forced to run full synthesis on each iteration of the design. For complex designs that involve many iterations and optimizations, the run-time of synthesis can be quite prohibitive .However, to achieve high performance; FPGA must be supported by efficient design methodology and optimization techniques. The motivation behind this work is to review different FPGA based design methodology and optimization techniques that can be employed to efficiently estimate hardware area utilized in terms of look up table (LUT'S) or configurable logic blocks (CLB'S).

Keyword: HW/SW Partitioning, Area Estimation, Latency Estimation

[1] Shi, C., Hwang, J., McMillan, S., Root, A., and Singh, V.,"A System Level Resource Estimation Tool for FPGAs",International Conference on Field Programmable Logic andApplications (FPL), 2004.

[2] C. Brandolese, W. Fornaciari, and F. Salice. "An AreaEstimation Methodology for FPGA Based Designs at SystemCLevel,"DAC'04, San Diego, California, USA, pp. 129 - 132, 2004.

[3] RoelMeeuws, "A Quantitative model for Hardware/Software partitioning," MSc thesis, Delft University of Technology, 2007.

[4] V. Srinivasan, S. Govindarajan, and R. Vemuri, "Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-FPGA architectures," IEEE Transactions on Very Large Scale Integration(VLSI) Systems, Vol. 9, no. 1, pp. 140–158, 2001.

[5] F. Vahid and D. D. Gajski, "Incremental hardware estimation during hardware/software functional partitioning," in Readings in hardware/software co-design, G. De Micheli, R. Ernest, and W.Wolf (eds.), Morgan Kaufmann, pp. 516–521, 2002.

[6] L. Yan, T. Srikanthan, and N. Gang, "Area and Delay Estimation for FPGA Implementation of Coarse-Grained Reconfigurable Architectures," LCTES, Ottawa, Ontario, Canada,pp.182–188, 2006.

[7] R. Enzler, T. Jeger, D. Cottet, and G. Troster, "High level area and performance estimation of hardware building blocks on FPGAs," FPL 2000, Villach, Austria, pp. 525–534, 2000.

[8] D. Kulkarni, Walid A. Najjar, R. Rinker and F. J. Kurdahi,"Compile-Time Area Estimation for LUT-Based FPGAs," ACMTODAES, Vol. 11, No. 1, pp. 104–122, 2006.

[9] P Bjureus, M. Millberg, and A. Jantsch, "FPGA resource and timing estimation from MATLAB execution traces," CODES 2002,Estes Park, Colorado, USA, pp. 31–36, 2002.

[10] L. M. Reyneri, F. Cucinotta, A. Serra, and L. Lavagno, "A hardware/software co-design flow and IP library based on Simulink," DAC '01, Las Vegas, Nevada, USA, pp. 593 - 598,2001.

Paper Type	:	Research Paper
Title	:	Medial Axis Transformation based Skeletonzation of Image Patterns using Image Processing Techniques
Country	:	India
Authors	:	Shivani Sharma, Maninder Kaur
	:	10.9790/0661-1340710

Abstract: The medial axis of an image pattern is the loci of all inscribed disks that touch two or more boundary points without crossing any of the boundaries. The medial axis transform (MAT) is a powerful representation for objects with inherent symmetry or near-symmetry. The medial axis of 2-D image patterns provides a conceptual design base, with transition to a detailed design occurring when the radius function is added to the medial axis or surface. To make such a design tool practicable, however, it is essential to be able to convert from an MAT format to a boundary representation of an object. In the proposed work, the medial axis transform has been extracted using the Euclidean distance transform based computation. The image pattern u prepared initially in binary form and then distance of each non-zero pixel to its closest zeroed pixel is computed. This process continues till the entire image pattern is scanned to its core.

Keywords: MAT -> Medial Axis Transform, EDT-> Euclidean Distance Transform, CCD-> Charge Coupled Device

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Paper Type	:	Research Paper
Title	:	Network Lifespan Maximization For Wireless Sensor Networks Using Nature-Inspired Elephant Based Swarm Optimization
Country	:	India
Authors	:	Chandramouli H., Dr. Somashekhar C. Desai
	:	10.9790/0661-1341119

Abstract: The robust and complex real-time applications and dramatically increased sensor capabilities may play a vital role in enhancing the lifespan of WSNs. On the other hand majority of WSNs operate on battery powered infrastructure, therefore in order to enhance the lifespan maximization a robust and highly efficient protocols are required to be developed that can effectively minimize the battery utilization and the overall computational as well as communication complexity also could be minimized. Optimizations required to be adopted at the Routing Layer, MAC Layer and the Radio Layer of the wireless sensor node. In this paper in order to achieve a better network performance an scheme of elephant swarm optimization has been implemented which enables optimization of routing algorithm, adaptive radio link optimization and balanced TDMA MAC scheduling. The proposed Elephant Based Swarm Optimization scheme is analyzed and compared with the popular LEACH and PSO Protocols and results proves that the EBSO algorithm is the best among PSO and LEACH schemes.

Keywords: Active node ratio, Cross-layer design, Elephant Based Swarm Optimization (EBSO), LEACH, Network lifespan, Particle Swarm Optimization (PSO).

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