iosr-JCE   Volume-11 ~ Issue-3

Abstract: The Full Adder circuit is an important component in application such as Digital Signal Processing (DSP) architecture, microprocessor, and microcontroller and data processing units. This paper discusses the evolution of full adder circuits in terms of lesser power consumption, higher speed. Starting with the most conventional 28 transistor full adder and then gradually studied full adders consisting of as less as 8 transistors. We have also included some of the most popular full adder cells like dynamic CMOS [9], Dual rail domino logic[14], Static Energy Recovery Full Adder (SERF) [7] [8], Adder9A, Adder9B, GDI based full adder.

Keywords : CMOS Transmission Gate (TG), Pass-Transistor Logic (PTL), Complementary Pass-transistor Logic (CPL), Gate Diffusion Input (GDI), Static Energy Recovery Full Adder (SERF), dynamic CMOS (D CMOS), Dual rail domino logic (DRD), Adder9A, Adder9B, GDI based full adder Power, Delay, Channel Length.

[1] Chandrakasan, R. Brodersen, ―Low Power Design‖, Kluwer Academic Publishers, 1995.

[2] A. M. Shams, and M. A. Bayoumi, ―A Novel High Performance CMOS 1-Bit Full Adder Cell‖, IEEE Transactions on Circuit and System, vol.47, NO. 5,May, 2000.

[3] J. H. Kang and J. B. Kim, ―Design of a Low Power CVSL Full Adder Using Low-Swing Technique‖, ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia.

[4] A. A. Khatibzadeh and K. Raahemifar, ―A Study and Comparison of Full Adder Cells based on the Standard Static CMOS Logic.‖, IEEE CCECE 2004 -CCGEI 2004, Niagara Falls, May 2004.

[5] S. M. Kang and Y. Leblebici, ―CMOS Digital Integrated Circuits: Analysis and Design‖, Third Edition, Tata McGraw-Hill Edition 2003, pp 307-316.

[6] A. Morgenshtein, A. Fish and A. Wagner, ―Gate-Diffusion Input(GDI): A Power-Efficient Method for Digital Combinational Circuits‖, IEEE Trans.VLSI Syst., pp. 566-581, Oct. 2002.

[7] I. Hassoune, D.Flandre, I. O'Connor and J. D. Legat, ―ULPFA: a new efficient design of a power aware full adder‖, IEEE Transactions on Circuits andSystems I-5438, 2008.

[8] R. Zimmermann and W. Fichter, ―Low –power logic styles: CMOS versus pass-transistor logic,‖ IEEE J. Solid-State Circuits, Vol. 32, July 1997,pp.1079-90

[9] N. Weste and K. Eshraghian, ―Principles of VLSI Design, A System Perspective‖, Reading, MA: Addison-Wesley, 1993.

[10] N. Zhuang and H. Wu, ―New Design of the CMOS Full Adder‖, IEEE J. Solid-State Circuits, vol. 27,no. 5,pp. 840-844, May 1992

Abstract: Routing traffic through multiple paths is known as multipath routing. There was considerable research in the area of multiple-path source routing to overcome the problem of jamming. Many jamming-aware approaches existed. This paper explores the jamming aware concept of [1] with empirical studies using NS2. Moreover it also explores the possibility of relaxing the assumption of [1] with respect to in-network inference of correlations among related variables. In this implementation the source node allocates traffic to the available paths based on the awareness of jamming details at nodes. The practical implementation makes use of portfolio selection as explored in [1] and tries to explore the in-network inference of correlations among estimated random variables. The algorithm used to achieve this ensures that all available paths are optimally utilized without congestion while maximizing throughput. The simulation results revealed that the network is capable of performing jamming aware allocation of traffic.

Index Terms–Multiple path source routing, traffic allocation, jamming, optimization, and in-network inference.

[1] Patrick Tague, Sidharth Nabar, James A. Ritcey, and Radha Poovendran, "Jamming-Aware Traffic Allocation for Multiple-Path Routing Using Portfolio Selection", IEEE/ACM TRANSACTIONS ON NETWORKING, VOL. 19, NO. 1, FEB 2011.

[2] R. Anderson, Security Engineering: A Guide to Building Dependable Distributed Systems. JohnWiley&Sons, Inc.,2001.

[3] J. Bellardo and S. Savage, "802.11 denial-of-service attacks: Real vulnerabilities and practical solutions," in Proc. USENIX Security Symposium, Washington, DC, Aug. 2003, pp. 15–28.

[4] D. J. Thuente and M. Acharya, "Intelligent jamming in wireless networks with applications to 802.11b and other networks," in Proc. 25thIEEE Communications Society Military Communications Conference (MILCOM'06), Washington, DC, Oct. 2006, pp. 1–7.

[5] G. Lin and G. Noubir, "On link layer denial of service in data wireless LANs," Wireless Communications and Mobile Computing, vol. 5, no. 3, pp. 273–284, May 2005.

[6] W. Xu, K. Ma, W. Trappe, and Y. Zhang, "Jamming sensor networks: Attack and defense strategies," IEEE Network, vol. 20, no. 3, pp. 41–47, May/Jun. 2006.

[7] R. Leung, J. Liu, E. Poon, A.-L. C. Chan, and B. Li, "MP-DSR: A QoSaware multi-path dynamic source routing protocol for wireless ad-hoc networks," in Proc. 26th Annual IEEE Conference on LocalComputer Networks (LCN'01), Tampa, FL, USA, Nov. 2001, pp. 132–141.

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[9] E. M. Sozer, M. Stojanovic, and J. G. Proakis, "Underwater acoustic networks," IEEE Journal of Oceanic Engineering, vol. 25, no. 1, pp. 72–83, Jan. 2000.

[10] A. D. Wood and J. A. Stankovic, "Denial of service in sensor networks," IEEE Computer, vol. 35, no. 10, pp. 54–62, Oct. 2002.

Abstract: Transport demand in most Indian cities has increased significantly due to increase in population as a result of both natural increase and migration from rural areas and smaller towns fast growth of India's population like other developing countries has trigger a greater need for used organized public transport system. Automation of bus transport has been gaining more importance because they provide accurate information of buses like reservation, air charges, route information, bus information etc anywhere and anytime. The dissertation has been divided into six modules based on the functionalities of the system namely, information system module, reservation system module. Administartive management system module, fleet management system module, and warehouse module and financial module. These modules have been designed to build up an integrated system to cover various aspects of automated bus transport management system. They provide full information about the bus enquiry, buses schedules, buses fairs, buses ticket reservation, buses time table enquiry.

[1]. S.L Bandarkar Dhanpat Rai & co (Eds.), Vehicle Transport Management.
[2]. G.V Rao Dhanpat Rai & co, principal of transportation and highway engineering.
[3]. Kumar Gaurav, Swati Agrawal and P.Krishna Reddy, Towards an It-based Bus Information System to Improve Bus Occupancy in Hyderabad, Proceedings of the 7th International Conference on Information Technology, CIT 2004, Hyderabad, India, December 2004. Pp.
[4]. S.Chaudhuri, Umeshwar Dayal, Vagrant (2001), Database Technology for decision support systems, IEEE Computer, pp.48-55, December 2001.
[5]. Delhi Transport Corporation.http://dtc.nic.in